RISC V core implementation using Verilog.
☆31Mar 27, 2021Updated 5 years ago
Alternatives and similar repositories for VLSI
Users that are interested in VLSI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Training Neural Networks using Analog circuits☆34Dec 6, 2020Updated 5 years ago
- Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes☆12Sep 23, 2023Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 5 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- Robot Control Library for Arduino☆10Sep 17, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VLSI Design of an 8 x 2 SRAM Array | Cadence Virtuoso☆12Feb 10, 2020Updated 6 years ago
- This repository contains openlane configuration and source files for tutorials that I created☆16Mar 5, 2024Updated 2 years ago
- Apple Silicon port of Isaac Lab with MLX training, Metal hot paths, and a mac-sim runtime for robotics research on macOS.☆13Mar 20, 2026Updated 7 months ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 7 years ago
- Source code for 'Beginning Robotics with Raspberry Pi and Arduino: Using Python and OpenCV' by Jeffrey Cicolani☆11Jan 29, 2022Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆140Nov 23, 2020Updated 5 years ago
- Robot IR Remote Library for Arduino☆10May 7, 2019Updated 7 years ago
- HDLBits-Solutions☆14May 27, 2022Updated 4 years ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Udemy's "Mastering Microcontroller and Embedded Driver Development (MCU1)" course by FastBit Embedded Brain Academy.☆17Aug 31, 2025Updated last year
- C++ library for BluetoothLE usage on MacOS or (soon) Windows☆11Oct 21, 2020Updated 6 years ago
- ☆11Dec 31, 2024Updated last year
- ☆18Jun 10, 2019Updated 7 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆15Feb 24, 2026Updated 8 months ago
- RV32I single cycle simulation on open-source software Logisim.☆23Oct 8, 2022Updated 4 years ago
- This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by …☆11May 11, 2023Updated 3 years ago
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆11Mar 7, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- source code☆14May 10, 2021Updated 5 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Build a spiking convolutional neural network in tensorflow for image recognitioon tasks☆11Apr 9, 2019Updated 7 years ago
- Repository for a 4-wheel robot car based on Arduino for the "Elegoo Smart Robot Car Kit V3.0 Plus" and similar ones.☆13Dec 20, 2022Updated 3 years ago
- Implementation of a RISC-V CPU in Verilog.☆21Jun 27, 2026Updated 4 months ago
- Parameterized Booth Multiplier in Verilog 2001☆52Oct 30, 2022Updated 4 years ago
- N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28n…☆23Jun 14, 2026Updated 4 months ago
- Source code repository for LetsRobot telepresence robots (using Arduino, Rasberry Pi, and Unity3D)☆18Dec 3, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Yahboom RTR self balance smart robot car for Arduino☆21Apr 12, 2021Updated 5 years ago
- verilog/FPGA hardware description for very simple GPU☆17Apr 9, 2019Updated 7 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆15Jul 24, 2020Updated 6 years ago
- FPGA-Based Logic Analyzer☆15Apr 18, 2016Updated 10 years ago
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆20Jun 3, 2023Updated 3 years ago