spider-tronix / VLSILinks
RISC V core implementation using Verilog.
☆26Updated 4 years ago
Alternatives and similar repositories for VLSI
Users that are interested in VLSI are comparing it to the libraries listed below
Sorting:
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆51Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- ☆41Updated last year
- An 8 input interrupt controller written in Verilog.☆28Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- Structured UVM Course☆45Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- Basic RISC-V Test SoC☆139Updated 6 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆32Updated 3 years ago
- ☆12Updated 4 months ago
- ☆17Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- This is a detailed SystemVerilog course☆113Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- ☆21Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆17Updated 4 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆56Updated 2 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆65Updated 8 years ago