This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
☆55Feb 22, 2022Updated 4 years ago
Alternatives and similar repositories for OpenSource_Physical_Design
Users that are interested in OpenSource_Physical_Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆99Sep 17, 2022Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆65Jul 9, 2021Updated 5 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆24Jul 7, 2021Updated 5 years ago
- ☆43Nov 28, 2022Updated 3 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- RTL to GDS via Cadence Tools☆20May 17, 2022Updated 4 years ago
- ☆15Sep 27, 2022Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆140Nov 23, 2020Updated 5 years ago
- FIFO implementation with different clock domains for read and write.☆17Aug 17, 2021Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆85Nov 26, 2020Updated 5 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆19Sep 15, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆170Apr 1, 2026Updated 6 months ago
- ☆42Feb 28, 2022Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆52Dec 6, 2020Updated 5 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆20Nov 11, 2025Updated 11 months ago
- ☆56Oct 24, 2022Updated 4 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆16Jul 6, 2025Updated last year
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆27Jul 21, 2025Updated last year
- ☆29May 9, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SKY130 ReRAM and examples (SkyWater Provided)☆47Apr 20, 2022Updated 4 years ago
- SystemVerilog RTL Linter for YoSys☆25Nov 22, 2024Updated last year
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 5 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 3 years ago
- This repository is created for conducting RISC-V 5-day workshops☆24Jul 29, 2020Updated 6 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆179Oct 21, 2023Updated 3 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Feb 16, 2022Updated 4 years ago
- ☆13Apr 12, 2023Updated 3 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆17Mar 31, 2021Updated 5 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆12Jan 23, 2026Updated 9 months ago
- ☆14Oct 5, 2024Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Design of miller compensated 2 stage opamp using open source SKY130PDK☆19Jun 18, 2025Updated last year
- Debug waveforms with GDB☆33Nov 12, 2025Updated 11 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆91May 2, 2021Updated 5 years ago