ekiwi / rtl-fuzz-lab
A Modular Open-Source Hardware Fuzzing Framework
☆32Updated 3 years ago
Alternatives and similar repositories for rtl-fuzz-lab:
Users that are interested in rtl-fuzz-lab are comparing it to the libraries listed below
- rfuzz: coverage-directed fuzzing for RTL research platform☆102Updated 2 years ago
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated last year
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated last year
- Code repository for Coppelia tool☆22Updated 4 years ago
- Testing processors with Random Instruction Generation☆31Updated last week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated this week
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆14Updated last month
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- ☆32Updated last week
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- RTLCheck☆19Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆17Updated 7 months ago
- ☆15Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 4 years ago
- ☆12Updated 3 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆16Updated 3 months ago
- ☆27Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ☆17Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- ☆17Updated 8 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 3 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆11Updated 3 years ago