Alternatives and similar repositories for Coppelia

Users that are interested in Coppelia are comparing it to the libraries listed below

• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆107Updated 3 years ago
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆19Updated 2 years ago
• HWSec-UNC / Sylvia
  ☆16Updated last month
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆20Updated 5 months ago
• iscas-tis / CHA
  ☆19Updated last year
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• efeslab / asplos22-hardware-debugging-artifact
  ☆12Updated last year
• efeslab / hardware-bugbase
  ☆18Updated last year
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated last month
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago
• ics-jku / spinalfuzz
  Fuzzing for SpinalHDL
  ☆16Updated 2 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆57Updated this week
• dian-lun-lin / GenFuzz
  GPU-enabled Hardware Fuzzer using Genetic Algorithm
  ☆17Updated 2 years ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆13Updated 3 weeks ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 2 weeks ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• ymanerka / ccicheck
  ☆9Updated 9 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆79Updated this week
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• compsec-snu / difuzz-rtl
  ☆88Updated last year
• yaohsiaopid / rtl2uspec
  ☆11Updated last week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆39Updated this week