Convolutional Neural Network RTL-level Design
☆75Oct 22, 2021Updated 4 years ago
Alternatives and similar repositories for CNN-Implementation-in-Verilog
Users that are interested in CNN-Implementation-in-Verilog are comparing it to the libraries listed below
Sorting:
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 4 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆164Dec 13, 2020Updated 5 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆578Feb 19, 2021Updated 5 years ago
- ☆20Apr 7, 2021Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆195Mar 20, 2024Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆11Jun 25, 2025Updated 8 months ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆14Jan 6, 2019Updated 7 years ago
- ☆11Oct 10, 2019Updated 6 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Jun 30, 2020Updated 5 years ago
- Generator of verilog description for FPGA MobileNet implementation☆184Jun 23, 2022Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- FPGA☆159Jun 29, 2024Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆252Dec 29, 2018Updated 7 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆582Jun 18, 2018Updated 7 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆15Sep 9, 2023Updated 2 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆18Oct 11, 2019Updated 6 years ago
- FPGA实现动态图像识别☆23Jul 31, 2020Updated 5 years ago
- IC implementation of Systolic Array for TPU☆340Oct 21, 2024Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Oct 14, 2022Updated 3 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆180Apr 10, 2023Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆182Jun 20, 2024Updated last year