boaaaang / CNN-Implementation-in-Verilog
Convolutional Neural Network RTL-level Design
☆51Updated 3 years ago
Alternatives and similar repositories for CNN-Implementation-in-Verilog
Users that are interested in CNN-Implementation-in-Verilog are comparing it to the libraries listed below
Sorting:
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆177Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆150Updated 10 months ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆148Updated 2 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆36Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆159Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆196Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆175Updated 6 months ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆147Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆31Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆109Updated this week
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆110Updated 4 years ago
- Implementation of CNN using Verilog☆211Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆179Updated 7 years ago
- FPGA☆154Updated 10 months ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- verilog实现systolic array及配套IO☆8Updated 5 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆45Updated 2 months ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆13Updated 3 years ago
- some interesting demos for starters☆79Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- IC implementation of Systolic Array for TPU☆239Updated 6 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆200Updated last year
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago