Convolutional Neural Network RTL-level Design
☆89Oct 22, 2021Updated 5 years ago
Alternatives and similar repositories for CNN-Implementation-in-Verilog
Users that are interested in CNN-Implementation-in-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆612Feb 19, 2021Updated 5 years ago
- Implementation of CNN using Verilog☆249Oct 13, 2017Updated 9 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆199Mar 20, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ES-203 Computer Organization & Architecture CNN on FPGA board☆18Feb 23, 2022Updated 4 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆169Dec 13, 2020Updated 5 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Senior Design Project at UW-Madison ECE☆17May 4, 2023Updated 3 years ago
- Generator of verilog description for FPGA MobileNet implementation☆191Jun 23, 2022Updated 4 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 4 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件,并在 ARM+FPGA 完成项目部署,实现通过摄取图片并通过 ARM+FPGA 综合部署和加速识别算法,并通过显示驱动,在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 4 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆202Apr 10, 2023Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆198Jun 20, 2024Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- SNN on FPGA☆13Apr 26, 2022Updated 4 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- Implementing a LeNet-5 network to achieve hand-written digital's recognition with pure verilog.☆11Dec 9, 2024Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- FPGA project☆251Apr 5, 2022Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- IC implementation of Systolic Array for TPU☆382Oct 21, 2024Updated 2 years ago
- ☆17Jul 10, 2024Updated 2 years ago
- FPGA☆159Jun 29, 2024Updated 2 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆595Jun 18, 2018Updated 8 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 6 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆18May 17, 2024Updated 2 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 6 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆53Oct 14, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆262Dec 29, 2018Updated 7 years ago
- ☆21Apr 7, 2021Updated 5 years ago
- SJTU MST3314 course project (CNN). A binary classification convolutional neural network in Verilog.☆15Mar 8, 2026Updated 7 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆53Jun 24, 2022Updated 4 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆267Apr 10, 2023Updated 3 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆375May 2, 2023Updated 3 years ago