Hand written number classification done in hardware (De1-SoC board) using neural networks
☆25Mar 21, 2018Updated 8 years ago
Alternatives and similar repositories for FPGA-Mnist
Users that are interested in FPGA-Mnist are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆18Oct 11, 2019Updated 6 years ago
- ☆10Nov 22, 2022Updated 3 years ago
- using xilinx xc6slx45 to implement mnist net☆83Jul 5, 2018Updated 7 years ago
- ☆11Jul 26, 2017Updated 8 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- [ACL'22] Training-free Neural Architecture Search for RNNs and Transformers☆14May 26, 2024Updated last year
- Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks☆623Jan 3, 2020Updated 6 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- Quantum Binary Neural Networks☆16Oct 20, 2019Updated 6 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆12Sep 30, 2022Updated 3 years ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆313Sep 7, 2022Updated 3 years ago
- ROS nodes for real-time motion planning and high-level control of an outdoor ground robot☆13Jun 24, 2019Updated 6 years ago
- Flappy Bird on Verilog☆16Jun 6, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An OS X flavored plymouth for Linux Ubuntu.☆11Dec 7, 2017Updated 8 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆16Dec 14, 2021Updated 4 years ago
- Generator of verilog description for FPGA MobileNet implementation☆187Jun 23, 2022Updated 3 years ago
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 10 years ago
- ☆13Mar 31, 2017Updated 9 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Apr 10, 2026Updated 3 weeks ago
- ☆16Mar 9, 2021Updated 5 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 5 years ago
- Amateur Radio Exam notes for Singapore☆38May 11, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 7 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated last year
- Python on Zynq FPGA for Convolutional Neural Networks☆623May 15, 2018Updated 7 years ago
- Mirror of git://git.zerfleddert.de/usb-driver☆20Aug 9, 2013Updated 12 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆61Feb 10, 2026Updated 2 months ago
- Generate Micro-Doppler signature of human motion by radar☆12Jul 2, 2023Updated 2 years ago
- ☆16Nov 6, 2023Updated 2 years ago
- 兰州理工大学毕业论文LaTeX模板 LaTeX Thesis Template for Lanzhou University of Technology☆12Jun 5, 2018Updated 7 years ago
- Where programmers share ideas and help each other grow☆12Jun 9, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- CANoolder: CAN to 3.3V logic level interface. Dumb. Cheap. Simple. Pick 3.☆15Feb 14, 2018Updated 8 years ago
- ☆11Jun 26, 2020Updated 5 years ago
- ☆13Mar 11, 2023Updated 3 years ago
- CNN Baseline for Image Compression☆10Nov 11, 2018Updated 7 years ago
- HW-GPT-Bench: Hardware-Aware Architecture Benchmark for Language Models☆24Dec 6, 2024Updated last year
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- Unified Coverage Interoperability Standard (UCIS)☆14Jan 28, 2026Updated 3 months ago