Johnny-Zou / FPGA-Mnist
Hand written number classification done in hardware (De1-SoC board) using neural networks
☆24Updated 7 years ago
Alternatives and similar repositories for FPGA-Mnist:
Users that are interested in FPGA-Mnist are comparing it to the libraries listed below
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆62Updated 8 months ago
- ☆63Updated 6 years ago
- PYNQ Composabe Overlays☆71Updated 10 months ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- ☆10Updated 7 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆107Updated 5 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆17Updated 5 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 5 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆30Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆51Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆54Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- ☆31Updated 5 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 10 months ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- A 2D convolution hardware implementation written in Verilog☆44Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- SDRAM controller with AXI4 interface☆91Updated 5 years ago