☆37May 29, 2021Updated 5 years ago
Alternatives and similar repositories for FPGA_network
Users that are interested in FPGA_network are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件，并在 ARM＋FPGA 完成项目部署，实现通过摄取图片并通过 ARM＋FPGA 综合部署和加速识别算法，并通过显示驱动，在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- 使用verilog实现流水线 FFT☆16Jul 1, 2024Updated last year
- some interesting demos for starters☆97Dec 2, 2022Updated 3 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆597Feb 19, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PointPillars TensorRT version pretrained on MMDetection3d with WaymoOpenDataset☆23Aug 11, 2022Updated 3 years ago
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- Generator of verilog description for FPGA MobileNet implementation☆186Jun 23, 2022Updated 3 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆49May 4, 2020Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated last year
- Zynq/FPGA实现CNN手写数字(0-9)识别☆41Dec 14, 2024Updated last year
- YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board☆23Jul 30, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 4 years ago
- This repository contains codes used for our Globecom 2018 paper "Spatial Zadoff-Chu modulation for rapid beam alignment in mmWave phased …☆14Mar 21, 2019Updated 7 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆21Apr 11, 2022Updated 4 years ago
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆12Apr 15, 2023Updated 3 years ago
- Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision☆12Jan 19, 2026Updated 4 months ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆12Mar 12, 2021Updated 5 years ago
- ☆11Nov 22, 2022Updated 3 years ago
- The DDR Test Firmware for LicheeTang20K.☆17Jun 20, 2023Updated 2 years ago
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 11 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆201Oct 9, 2019Updated 6 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆30Mar 13, 2025Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- ☆13Jul 10, 2024Updated last year
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆27Dec 17, 2022Updated 3 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆195Apr 10, 2023Updated 3 years ago
- ☆13Jun 4, 2020Updated 6 years ago
- Use Matlab to simulate in LT Spice, acquire results and plot☆18Oct 22, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA implementation of Semi Global Matching algorithm, using High Level Synthesis☆19Dec 8, 2022Updated 3 years ago
- FPGA☆160Jun 29, 2024Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆14Aug 26, 2021Updated 4 years ago
- We propose a method MPCF.☆34May 19, 2026Updated 3 weeks ago
- 2023集创赛紫光同创杯一等奖项目☆176Jan 7, 2024Updated 2 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- ☆13Apr 15, 2025Updated last year