Marco-Winzker / NN_Pattern_FPGA
Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA implementation with VHDL.
☆23Updated 11 months ago
Alternatives and similar repositories for NN_Pattern_FPGA:
Users that are interested in NN_Pattern_FPGA are comparing it to the libraries listed below
- ☆28Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆34Updated 11 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆14Updated 2 years ago
- FPGA Design of a Neural Network for Color Detection☆75Updated 2 months ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆55Updated 2 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆107Updated 5 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆34Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆31Updated 4 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆54Updated 5 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆59Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 4 months ago
- AMD Xilinx University Program Vivado tutorial☆39Updated 2 years ago
- FFT algorithm for fpga☆19Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- PYNQ Composabe Overlays☆71Updated 10 months ago
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- An implementation of the CORDIC algorithm in Verilog.☆93Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆51Updated last year
- Vitis Model Composer Examples and Tutorials☆98Updated last week
- CNN-to-FPGA-framework for small CNN, written in VHDL and Python☆22Updated 3 years ago