Project Trellis database
☆16Oct 12, 2026Updated 3 weeks ago
Alternatives and similar repositories for prjtrellis-db
Users that are interested in prjtrellis-db are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Benchmarks for Yosys development☆25Feb 17, 2020Updated 6 years ago
- Collection of test cases for Yosys☆18Jan 4, 2022Updated 4 years ago
- SymbiFlow Website Source☆12Apr 7, 2022Updated 4 years ago
- Qucs-Help documentation☆10Jul 25, 2018Updated 8 years ago
- GUI for SymbiYosys☆19Aug 4, 2026Updated 3 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A padring generator for ASICs☆27May 17, 2023Updated 3 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- USB Full-Speed core written in migen/LiteX☆17Sep 2, 2019Updated 7 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆18Mar 19, 2026Updated 7 months ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆39Nov 13, 2025Updated 11 months ago
- Test/demo waveform datasets for libscopehal and glscopeclient☆12Oct 5, 2023Updated 3 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 8 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆38Oct 29, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Betrusted embedded controller (UP5K)☆50Dec 22, 2023Updated 2 years ago
- Prim-Dijkstra Revisited☆10Jun 9, 2021Updated 5 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 8 years ago
- ☆29Dec 16, 2020Updated 5 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- Open Source Detailed Placement engine☆13Feb 19, 2020Updated 6 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆33Jan 22, 2022Updated 4 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 7 years ago
- 数字图像处理彩色图像复原☆15Jun 21, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 100道图像处理算法中文版☆14Jul 17, 2020Updated 6 years ago
- 1st Testwafer for LibreSilicon☆28Aug 2, 2019Updated 7 years ago
- Nix channel with FPGA development tools☆13Dec 21, 2020Updated 5 years ago
- The source code that empowers OpenROAD Cloud☆15Jun 29, 2020Updated 6 years ago
- Documenting the Lattice ECP5 bit-stream format.☆477Updated this week
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 7 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- A multiply core generator☆16Jun 25, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆32Jul 12, 2024Updated 2 years ago
- A Qt5 based free VLSI development tool☆31Jun 24, 2018Updated 8 years ago
- A low cost FPGA development board for absolute newbies☆18Jan 2, 2019Updated 7 years ago
- nextpnr portable FPGA place and route tool☆21Aug 21, 2024Updated 2 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 6 months ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- A Verilog Synthesis Regression Test☆40Jan 19, 2026Updated 9 months ago