a simple C-to-Verilog compiler
☆51Apr 16, 2017Updated 9 years ago
Alternatives and similar repositories for cynth
Users that are interested in cynth are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain☆13Nov 24, 2015Updated 10 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- Experimental graphic editor for open FPGAs.☆50Mar 29, 2016Updated 10 years ago
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆20Apr 17, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simplified design of an analog keypad matrix interface and demo thereof☆16May 27, 2021Updated 5 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano☆13Apr 15, 2019Updated 7 years ago
- symbolic execution engine for brainfuck because lol☆14Feb 5, 2017Updated 9 years ago
- Superoptimizer using the z3 SMT solver☆17Nov 1, 2025Updated 10 months ago
- C code browser☆24Aug 11, 2018Updated 8 years ago
- A circuit toolkit☆108Feb 23, 2020Updated 6 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Jul 11, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Docker image for running Vivado in a 64-bit Debian Jessie container☆13Mar 17, 2018Updated 8 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated 2 years ago
- Evoker is a graphical tool for plotting genotype intensity data in order to assess quality of genotype calls. It implements a compact, bi…☆13Dec 21, 2017Updated 8 years ago
- The excellent Diolan bootloader modified to use standard (non-extended) instruction set and still fit in 1 kB bootblock☆10Oct 6, 2023Updated 2 years ago
- Library of additional parts for KiCad for use with Sakura-IT projects☆25Dec 1, 2023Updated 2 years ago
- Object-Oriented Programming☆12Aug 26, 2021Updated 5 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆42Mar 7, 2025Updated last year
- ☆12Sep 26, 2021Updated 5 years ago
- Sample minimal Vivado project for Parallella FPGA☆46May 15, 2016Updated 10 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- An attempt at a small Verilog implementation of the original Apple 1 on an FPGA☆153Sep 22, 2025Updated last year
- Ice40 open source HDMI examples on BlackIce II☆12May 12, 2022Updated 4 years ago
- bits and bobs for hacking on certain variants of the TM155 mouse (mainly TeckNet M009-V2)☆13Jan 18, 2019Updated 7 years ago
- Tutorial/starter code for setting up GCC for PSOC5 (ARM) in an open-source baremetal configuration.☆33Nov 3, 2014Updated 11 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Mar 2, 2023Updated 3 years ago
- ZyncMV is an open source machine/computer vision platform using the Xilinx Zync FPGA+ ARM Cortex A9 SoC☆21Feb 12, 2017Updated 9 years ago
- "My 5-Year IoT Mission" presentation at Hackware 3 Dec 2019☆10Dec 3, 2019Updated 6 years ago
- ☆19Jul 7, 2016Updated 10 years ago
- Reed-Solomon Codec☆11Dec 21, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- small board to convert linear 3 pin regulator to switching regulator (TO220 compatible, eg 7805)☆11Oct 8, 2015Updated 10 years ago
- Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx☆95Jun 10, 2015Updated 11 years ago
- Makefiles for using EFM8 microcontrollers with SDCC☆11Apr 30, 2018Updated 8 years ago
- ☆55Apr 25, 2017Updated 9 years ago
- ILAng documentation☆12Nov 2, 2025Updated 10 months ago
- Fuzz testing for Dafny☆12Jul 7, 2022Updated 4 years ago
- FPGA Design Suite based on C to Verilog design flow.☆250Apr 5, 2019Updated 7 years ago