oshears / SNN-FPGA-Implementation
☆14Updated 3 years ago
Alternatives and similar repositories for SNN-FPGA-Implementation:
Users that are interested in SNN-FPGA-Implementation are comparing it to the libraries listed below
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆21Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆32Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆56Updated last year
- A repository FPGA-friendly SNN models☆32Updated 3 years ago
- Spiking Neural Network RTL Implementation☆49Updated 3 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆20Updated 6 years ago
- ☆17Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆53Updated 3 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆48Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆34Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆13Updated 3 years ago
- Spiking Neural Network Accelerator☆12Updated 2 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆16Updated 4 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆13Updated 3 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆10Updated last year
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆12Updated last year
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆24Updated 5 years ago
- ☆24Updated 2 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆19Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- FPGA Design of a Spiking Neural Network.☆34Updated 8 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆23Updated 4 years ago
- ☆44Updated 11 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆46Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆26Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago