bol-edu / 2022-fall-ntu

Related projects: ⓘ

• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆66Updated 2 years ago
• sazczmh / PYNQ_Workshop
  ☆39Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆33Updated 5 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆18Updated 3 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆18Updated 2 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆17Updated 11 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆83Updated 4 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆28Updated 5 years ago
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆36Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆121Updated 4 years ago
• CHNLeo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆60Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆58Updated 5 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆43Updated 4 years ago
• Microdent / Handwritten_Mathematical_Calculator_on_FPGA
  A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.
  ☆34Updated 4 years ago
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆74Updated 5 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆81Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• JF-Tan / Takk_Zynq_Labs
  This is just for Takk_Zynq_Labs test.
  ☆26Updated 2 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆10Updated 3 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆12Updated 5 years ago
• BIGWJZ / VLSI-DSP-Review
  ☆42Updated 4 years ago
• vincent08tw / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆17Updated 3 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆45Updated 2 years ago
• GJigar / ZYNQ_CNN
  ☆15Updated 2 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆14Updated last year
• ChunxuGuo / SummerSchool2022
  ☆57Updated last year
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆92Updated 5 months ago
• OpenHEC / SNN-simulator-on-PYNQcluster
  ☆81Updated 4 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆20Updated 2 years ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆13Updated 5 years ago