☆36Sep 17, 2024Updated last year
Alternatives and similar repositories for 2022-fall-ntu
Users that are interested in 2022-fall-ntu are comparing it to the libraries listed below
Sorting:
- ☆13Dec 10, 2022Updated 3 years ago
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated last year
- ASIC Design kit for Skywater 130 for use with mflowgen☆14Mar 12, 2023Updated 2 years ago
- some interesting demos for starters☆94Dec 2, 2022Updated 3 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆22Apr 20, 2022Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- Fast Floating Point Operators for High Level Synthesis☆24Feb 23, 2023Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated last year
- ☆18Feb 3, 2022Updated 4 years ago
- UCSD CSE 237D Spring '20 Course Project☆19Sep 4, 2023Updated 2 years ago
- ☆10Aug 30, 2024Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆85Nov 26, 2025Updated 3 months ago
- Computer-Aided VLSI System Design☆23Oct 24, 2024Updated last year
- Codes to implement MobileNet V2 in a FPGA☆30Dec 21, 2020Updated 5 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis☆27Jun 24, 2022Updated 3 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Apr 12, 2021Updated 4 years ago
- IC implementation of Systolic Array for TPU☆340Oct 21, 2024Updated last year
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- IC Contest☆44Mar 28, 2023Updated 2 years ago
- Embedded Microprocessor System Design using FPGAs 1. edition ISBN:☆12Apr 1, 2025Updated 11 months ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆87May 30, 2021Updated 4 years ago
- Robust PCA: PCP, Stable PCP, PCP with compressed data, IRCUR☆12Dec 19, 2021Updated 4 years ago
- ☆13Jan 8, 2020Updated 6 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- ☆12Jun 25, 2023Updated 2 years ago
- LTE Turbo Decoder using BCJR algorithm☆10Apr 8, 2018Updated 7 years ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆39Oct 13, 2023Updated 2 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆92Apr 26, 2025Updated 10 months ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- Lifelong machine learning is a novel machine learning paradigm which continually learns tasks and accumulates knowledge for reusing. The …☆10Sep 15, 2019Updated 6 years ago
- ☆12Feb 23, 2022Updated 4 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- bare minimum chess program☆11Sep 16, 2020Updated 5 years ago
- Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817☆12Nov 10, 2023Updated 2 years ago