Alternatives and similar repositories for 2022-fall-ntu

Users that are interested in 2022-fall-ntu are comparing it to the libraries listed below

• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆143Updated 7 months ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆177Updated 6 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆236Updated 2 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆121Updated last year
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆123Updated 5 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆92Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 7 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆122Updated 4 months ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆159Updated 9 months ago
• dldldlfma / super_small_toy_tpu
  ☆45Updated 4 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆139Updated 10 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆50Updated 6 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆39Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆109Updated 5 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆142Updated 6 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆60Updated 3 years ago
• skycrapers / AM-Lib
  ☆31Updated 2 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆196Updated 8 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆44Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆78Updated 3 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆166Updated 6 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆90Updated 5 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆41Updated 2 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 5 years ago
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆218Updated last year
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆108Updated 11 months ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆68Updated 11 months ago