Yikai-coder / HITSZ-DLA-2021
哈尔滨工业大学(深圳)2021年球季学期深度学习体系结构实验
☆13Updated 2 years ago
Alternatives and similar repositories for HITSZ-DLA-2021
Users that are interested in HITSZ-DLA-2021 are comparing it to the libraries listed below
Sorting:
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- ☆18Updated 2 years ago
- ☆26Updated 9 months ago
- ☆26Updated last month
- RTL generator for SpGEMM☆12Updated 4 years ago
- Vivado HLS study notes, courses, documents.☆12Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ☆11Updated last month
- ☆35Updated last month
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 9 months ago
- ☆20Updated 2 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆20Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆31Updated 3 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 10 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆12Updated last month
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆27Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- An FPGA Accelerator for Transformer Inference☆81Updated 3 years ago
- note about IC knowledge☆9Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆42Updated last year
- ☆12Updated last year
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆13Updated 5 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆23Updated last year