RicoLi424 / CNN-Digit-Recognition-Accelerated-on-FPGA
A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA
☆17Updated 2 years ago
Alternatives and similar repositories for CNN-Digit-Recognition-Accelerated-on-FPGA:
Users that are interested in CNN-Digit-Recognition-Accelerated-on-FPGA are comparing it to the libraries listed below
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆34Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆15Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆28Updated last year
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- 3×3脉动阵列乘法器☆38Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆36Updated 2 years ago
- ☆13Updated last year
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- LSTM neural network (verilog)☆13Updated 6 years ago
- ☆14Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆44Updated 5 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- Nuclei E203 with yolo accelerator based on xc7k325☆10Updated 7 months ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆57Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆77Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆11Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- syn script for DC Compiler☆12Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆32Updated 5 years ago
- ☆18Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆26Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- ☆29Updated 5 years ago