OpenHEC / SNN-simulator-on-PYNQcluster
☆88Updated 5 years ago
Alternatives and similar repositories for SNN-simulator-on-PYNQcluster:
Users that are interested in SNN-simulator-on-PYNQcluster are comparing it to the libraries listed below
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated last month
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆182Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆148Updated last year
- A Spiking neural network simulator NEST base on FPGA‘s cluster(LIF NEURON)☆17Updated 5 years ago
- 中文:☆97Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆175Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆55Updated 2 years ago
- Spiking Neural Network RTL Implementation☆55Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- An LeNet RTL implement onto FPGA☆45Updated 6 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆191Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆154Updated 5 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆35Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆94Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆141Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- A repository FPGA-friendly SNN models☆32Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆50Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆96Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- FPGA☆152Updated 9 months ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- ☆64Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆38Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆148Updated 9 months ago