ChunxuGuo / SummerSchool2022Links
☆63Updated 3 years ago
Alternatives and similar repositories for SummerSchool2022
Users that are interested in SummerSchool2022 are comparing it to the libraries listed below
Sorting:
- some interesting demos for starters☆93Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆156Updated last year
- 一个开源的FPGA神经网络加速器。☆185Updated 2 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆175Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆148Updated 7 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆84Updated 9 months ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆217Updated 2 months ago
- Nuclei E203 with yolo accelerator based on xc7k325☆19Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆124Updated 5 months ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆24Updated 2 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆87Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆237Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆110Updated 11 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆219Updated last year
- ☆14Updated 2 years ago
- FPGA☆159Updated last year
- ☆16Updated 3 years ago
- ☆10Updated 4 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- PYNQ学习资料☆174Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- FPGA project☆234Updated 3 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆138Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Updated last year
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- ☆45Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆46Updated 3 years ago