strath-sdr / rfsoc_qsfp_offload
RFSoC QSFP Data Offload Design with GNU Radio
☆15Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for rfsoc_qsfp_offload
- Python productivity for RFSoC platforms☆57Updated 6 months ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆91Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆11Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆26Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- ☆18Updated 3 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆69Updated 4 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆56Updated 4 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆20Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆31Updated last year
- Companion Jupyter Notebooks for the RFSoC-Book.☆147Updated last year
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆87Updated 5 months ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆24Updated 2 months ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- pynq framework for antsdr☆33Updated 5 months ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆37Updated 2 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆21Updated last month
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆54Updated last year
- MATLAB toolbox for ADI transceiver products☆57Updated this week
- Vivado build system☆71Updated this week
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆18Updated last year
- HDL code for a complex multiplier with AXI stream Interface☆13Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆45Updated 8 months ago
- Board files to build the ZCU111 PYNQ image☆17Updated 2 years ago
- RFNoC out-of-tree module for a channelizer☆15Updated 6 years ago