Alternatives and similar repositories for Limago:

Users that are interested in Limago are comparing it to the libraries listed below

• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆83Updated last week
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆206Updated last year
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆147Updated 9 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆160Updated this week
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆104Updated 3 years ago
• ucsdsysnet / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆193Updated last year
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆115Updated 4 months ago
• fpgasystems / Coyote
  Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…
  ☆248Updated 3 weeks ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆314Updated this week
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆47Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆255Updated last year
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆66Updated 4 months ago
• Xilinx / HLS_packet_processing
  ☆45Updated 5 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆168Updated last year
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 8 months ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆49Updated 9 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆245Updated 3 months ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 3 months ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆62Updated 6 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆123Updated 2 years ago
• Xilinx / open-nic
  AMD OpenNIC Project Overview
  ☆251Updated 2 years ago
• oprecomp / DDR4_controller
  ☆55Updated 4 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆74Updated 6 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆108Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated this week
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆78Updated 3 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆116Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆146Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago