lizardll / ScalaBFS
A Scalable BFS Accelerator on FPGA-HBM Platform
☆13Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for ScalaBFS
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 9 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- ☆23Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆21Updated 2 years ago
- ☆10Updated last year
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 2 years ago
- ☆25Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆29Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Heterogenous ML accelerator☆16Updated last month
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆16Updated 9 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆17Updated 7 months ago
- DASS HLS Compiler☆27Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆38Updated 6 months ago
- ☆21Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆16Updated 2 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆21Updated 4 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- ☆15Updated last year
- ☆33Updated 3 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago