Daikon-Sun / Physical-Design-for-Nanometer-ICs
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
☆40Updated 6 years ago
Alternatives and similar repositories for Physical-Design-for-Nanometer-ICs:
Users that are interested in Physical-Design-for-Nanometer-ICs are comparing it to the libraries listed below
- VLSI EDA Global Router☆72Updated 7 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- DATC RDF☆50Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆133Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆102Updated last year
- DATC Robust Design Flow.☆37Updated 5 years ago
- IDEA project source files☆106Updated 6 months ago
- ☆30Updated 4 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆41Updated 4 years ago
- ☆30Updated 3 years ago
- A parallel global router using the Galois framework☆27Updated last year
- A LEF/DEF Utility.☆28Updated 5 years ago
- ☆29Updated last year
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆121Updated 4 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆27Updated 3 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- GPU-based logic synthesis tool☆81Updated 9 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 9 months ago
- UCSD Detailed Router☆85Updated 4 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆51Updated 9 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆35Updated this week
- ☆25Updated last year
- EDA physical synthesis optimization kit☆53Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆46Updated 7 months ago
- ☆31Updated 3 years ago
- ☆43Updated last year