Alternatives and similar repositories for Physical-Design-for-Nanometer-ICs

Users that are interested in Physical-Design-for-Nanometer-ICs are comparing it to the libraries listed below

• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• twweeb / VLSI-Physical-Design-Automation
  Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
  ☆46Updated 4 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆136Updated 2 years ago
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆39Updated last month
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆58Updated last year
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆50Updated 5 months ago
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆127Updated last week
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• bu-icsg / TAP-2.5D
  ☆33Updated 4 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆126Updated 11 months ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• UMN-EDA / BeGAN-benchmarks
  ☆24Updated 2 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆170Updated last month
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆88Updated 4 years ago
• recurme / Mixed-Cell-Height_legalizer
  ☆10Updated 11 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆44Updated last year
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆27Updated last year
• ieee-ceda-datc / RDF-2020
  ☆13Updated 3 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆31Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆149Updated 2 months ago