Alternatives and similar repositories for PYNQ-ZU

Users that are interested in PYNQ-ZU are comparing it to the libraries listed below

• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 2 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• ATaylorCEngFIET / Vitis_Hero
  ☆28Updated 3 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆45Updated this week
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆19Updated 2 years ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆38Updated 3 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆41Updated 2 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆33Updated 3 years ago
• hibagus / 64pointFFTProcessor
  Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
  ☆30Updated 5 years ago
• strath-sdr / rfsoc_radio
  PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
  ☆37Updated 2 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆23Updated 3 years ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆29Updated 4 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆102Updated last week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 4 months ago
• jefflieu / HLS-Tiny-Tutorials
  This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
  ☆27Updated 3 years ago
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆32Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆57Updated last week
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 3 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆59Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 8 months ago