PYNQ-ZU, AUP UltraScale+ MPSoC academic board
☆30Oct 6, 2025Updated last year
Alternatives and similar repositories for PYNQ-ZU
Users that are interested in PYNQ-ZU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 4 years ago
- ☆15Aug 14, 2023Updated 3 years ago
- PYNQ Composabe Overlays☆81Jun 17, 2024Updated 2 years ago
- ☆10Sep 9, 2026Updated last month
- ☆20Sep 15, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆19Sep 14, 2025Updated last year
- ☆13Jul 14, 2020Updated 6 years ago
- Xilinx Hackathon 2017☆18May 15, 2023Updated 3 years ago
- ☆15Apr 11, 2025Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- Software control for CASPER FPGAs☆24Feb 5, 2026Updated 8 months ago
- 國立臺灣海洋大學碩博士論文 LaTeX 模板☆42Jul 13, 2026Updated 3 months ago
- CC-Cam: A diffuser camera based on Pynq-Z2☆20Oct 7, 2020Updated 6 years ago
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆34Nov 8, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Python productivity for RFSoC platforms☆105Sep 29, 2026Updated 2 weeks ago
- Train and deploy LUT-based neural networks on FPGAs☆122Jun 12, 2024Updated 2 years ago
- Business Rule Engine Hardware Accelerator☆15Jun 18, 2020Updated 6 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- AI Accelerators-SC23-tutorial Repository☆12Nov 12, 2023Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- Networking Overlay on PYNQ☆51Mar 5, 2019Updated 7 years ago
- ☆10May 20, 2022Updated 4 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Apr 20, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- pynq framework for antsdr☆37May 31, 2024Updated 2 years ago
- ☆10Mar 20, 2021Updated 5 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆93Jul 7, 2026Updated 3 months ago
- Board repo for the ZCU216 RFSOC☆35Jun 9, 2022Updated 4 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆42Jun 22, 2023Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆69Oct 23, 2020Updated 5 years ago
- ☆14Sep 28, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository is an implementation of the ViT paper from scratch with tutorials on model, dataloading, training, inference, finteuning,…☆12Aug 14, 2024Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Sep 28, 2026Updated 2 weeks ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Jun 29, 2022Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆122Jan 28, 2026Updated 8 months ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- ☆49Jun 18, 2024Updated 2 years ago
- Xilinx Alveo Graph Analytics Product repository☆14May 18, 2022Updated 4 years ago