Xilinx / PYNQ-ZULinks
PYNQ-ZU, AUP UltraScale+ MPSoC academic board
☆26Updated 2 weeks ago
Alternatives and similar repositories for PYNQ-ZU
Users that are interested in PYNQ-ZU are comparing it to the libraries listed below
Sorting:
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 3 years ago
- PYNQ Composabe Overlays☆73Updated last year
- Vitis Model Composer Examples and Tutorials☆105Updated last week
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- PYNQ support and examples for Kria SOMs☆111Updated last year
- Networking Overlay on PYNQ☆49Updated 6 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆105Updated 2 years ago
- ☆19Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL☆27Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- Verilog digital signal processing components☆150Updated 2 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆105Updated 2 years ago
- ☆28Updated 3 years ago
- ☆108Updated 6 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- Board files to build Ultra 96 PYNQ image☆157Updated 8 months ago
- A 2D convolution hardware implementation written in Verilog☆48Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆46Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- Board repo for the ZCU216 RFSOC☆29Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 5 months ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆83Updated 7 months ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago