Alternatives and similar repositories for metis_unicorn:

Users that are interested in metis_unicorn are comparing it to the libraries listed below

• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆62Updated 3 months ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆10Updated 8 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆37Updated 2 months ago
• ABKGroup / TritonRoute-WXL
  ☆26Updated 4 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆79Updated 6 months ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…
  ☆43Updated last year
• cure-lab / DeepGate2
  ☆14Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆66Updated 5 months ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆48Updated 3 weeks ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆40Updated last year
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆53Updated 4 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆36Updated 10 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆71Updated 7 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆98Updated 10 months ago
• Entropy-xcy / sns
  ☆14Updated 2 years ago
• ABKGroup / RosettaStone
  ☆23Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆23Updated 9 months ago
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆28Updated last year
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆39Updated 4 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆23Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆41Updated 2 weeks ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆54Updated 2 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆19Updated 4 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆82Updated 4 years ago