intelsdi-x / fpga-nova
Bring FPGA accelerators as a resources available through Docker containers for the OpenStack users.
☆16Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-nova
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆81Updated 3 weeks ago
- Provides Spatial with front-end support from popular machine learning frameworks☆32Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆15Updated 4 years ago
- Fibertree emulator☆11Updated last week
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 4 months ago
- ☆11Updated 3 months ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆47Updated 5 years ago
- ☆18Updated 3 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 3 months ago
- A Language for Closed-form High-level ARchitecture Modeling☆18Updated 4 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆30Updated last year
- HLS branch of Halide☆77Updated 6 years ago
- SmartNIC☆14Updated 5 years ago
- FPGA version of Rodinia in HLS C/C++☆31Updated 3 years ago
- research, experimentation and implementation of hardware-agnostic accelerated DL framework☆33Updated 2 weeks ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆53Updated 6 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Distributed Accelerator OS☆60Updated 2 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆22Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Learn NVDLA by SOMNIA☆26Updated 4 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago