Alternatives and similar repositories for Vitis-AWS-F1-Developer-Labs

Users that are interested in Vitis-AWS-F1-Developer-Labs are comparing it to the libraries listed below

• awslabs / aws-fpga-app-notes
  Application notes for the F1 EC2 Instance
  ☆88Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 5 months ago
• open-power / snap
  CAPI SNAP Framework Hardware and Software
  ☆109Updated 4 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 2 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated 11 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆213Updated 5 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆111Updated 2 months ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆69Updated 10 months ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• Xilinx / Get_Moving_With_Alveo
  For publishing the source for UG1352 "Get Moving with Alveo"
  ☆51Updated 5 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• Xilinx / SDAccel_Examples
  SDAccel Examples
  ☆357Updated 3 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆275Updated 2 months ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆200Updated 3 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆118Updated 4 years ago
• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆31Updated 2 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆166Updated last year
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆42Updated last week
• Xilinx / Xilinx_Base_Runtime
  ☆33Updated last year
• jingpu / Halide-HLS
  HLS branch of Halide
  ☆77Updated 7 years ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆321Updated 5 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆328Updated last week
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆150Updated 11 months ago