fpga-opencl-benchmarks / rodinia_fpgaLinks
Rodinia Benchmark Suite for OpenCL-based FPGAs
☆31Updated 2 years ago
Alternatives and similar repositories for rodinia_fpga
Users that are interested in rodinia_fpga are comparing it to the libraries listed below
Sorting:
- Spector: An OpenCL FPGA Benchmark Suite☆48Updated 6 years ago
- ☆88Updated 2 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆34Updated 8 months ago
- ☆30Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 4 months ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- ☆87Updated last year
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago