fpga-opencl-benchmarks / rodinia_fpgaLinks
Rodinia Benchmark Suite for OpenCL-based FPGAs
☆31Updated 2 years ago
Alternatives and similar repositories for rodinia_fpga
Users that are interested in rodinia_fpga are comparing it to the libraries listed below
Sorting:
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆49Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆88Updated 3 years ago
- ☆30Updated 6 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Updated this week
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆101Updated 7 months ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆52Updated 7 years ago
- ☆17Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Updated 7 years ago
- ☆22Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- ☆87Updated last year
- A DSL for Systolic Arrays☆83Updated 7 years ago
- Next generation CGRA generator☆118Updated this week
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 6 years ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- ☆82Updated 11 months ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated last week