fpga-opencl-benchmarks / rodinia_fpga
Rodinia Benchmark Suite for OpenCL-based FPGAs
☆30Updated last year
Related projects ⓘ
Alternatives and complementary repositories for rodinia_fpga
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Spector: An OpenCL FPGA Benchmark Suite☆43Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- ☆84Updated last year
- ☆87Updated 8 months ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 4 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆17Updated 8 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆47Updated 5 years ago
- FPGA version of Rodinia in HLS C/C++☆31Updated 3 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 6 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆64Updated 2 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- ☆57Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆32Updated 2 weeks ago
- ☆13Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- ☆27Updated 5 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 3 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing☆7Updated 5 years ago