Rodinia Benchmark Suite for OpenCL-based FPGAs
☆31Apr 11, 2023Updated 3 years ago
Alternatives and similar repositories for rodinia_fpga
Users that are interested in rodinia_fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Spector: An OpenCL FPGA Benchmark Suite☆50Feb 2, 2019Updated 7 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- Extracts static code features from opencl kernels to be used for machine learning.☆10Apr 30, 2021Updated 5 years ago
- Networking Template Library for Vivado HLS☆30Jul 12, 2020Updated 6 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- BLAS implementation for Intel FPGA☆79Nov 18, 2020Updated 5 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17May 4, 2020Updated 6 years ago
- Synthesizable Higher-Order Functions (Patterns) for C++☆18Oct 3, 2018Updated 7 years ago
- The implementation of HawkEye, our research system: "HawkEye: Efficient Fine-grained OS Support for Huge Pages" from ASPLOS 2019.☆21Aug 5, 2021Updated 5 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- ☆24Nov 10, 2020Updated 5 years ago
- SDAccel Examples☆360May 20, 2022Updated 4 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated last year
- Memory System Microbenchmarks☆65Feb 9, 2023Updated 3 years ago
- FPGA version of Rodinia in HLS C/C++☆44Dec 24, 2020Updated 5 years ago
- An FPGA NES emulator designed by a high level synthesis (HLS)☆16Jun 11, 2017Updated 9 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Jan 28, 2025Updated last year
- Sample program to compare calculation performance between CPU and GPU☆16Oct 27, 2016Updated 9 years ago
- ☆20Mar 25, 2019Updated 7 years ago
- A domain-specific language and compiler for image processing☆78Mar 20, 2021Updated 5 years ago
- Linux source code for ISCA 2020 paper "Enhancing and Exploiting Contiguity for Fast Memory Virtualization"☆22Oct 31, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆175Nov 7, 2023Updated 2 years ago
- ☆20Jul 26, 2021Updated 5 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- ☆15Jul 28, 2016Updated 10 years ago
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 6 years ago
- Highly-optimized spatially and temporally-blocked implementation of Diffusion 2D and 3D stencils for Intel FPGAs using OpenCL☆13Dec 25, 2023Updated 2 years ago
- OpenCL for Visual Studio Code☆40Updated this week
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- Bypassd is a novel I/O architecture that provides low latency access to shared SSDs.☆24May 14, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 11 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆388Jan 20, 2025Updated last year
- ☆14Feb 14, 2022Updated 4 years ago
- MLIR tools and dialect for GraphBLAS☆18Mar 30, 2022Updated 4 years ago
- Updated version of the XUP Workshops☆18Aug 10, 2018Updated 8 years ago
- Rich editor for SDFGs with included profiling and debugging, static analysis, and interactive optimization.☆22Dec 9, 2025Updated 9 months ago
- ☆23Nov 29, 2022Updated 3 years ago