Rodinia Benchmark Suite for OpenCL-based FPGAs
☆31Apr 11, 2023Updated 3 years ago
Alternatives and similar repositories for rodinia_fpga
Users that are interested in rodinia_fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Spector: An OpenCL FPGA Benchmark Suite☆50Feb 2, 2019Updated 7 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 4 years ago
- BLAS implementation for Intel FPGA☆78Nov 18, 2020Updated 5 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17May 4, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Synthesizable Higher-Order Functions (Patterns) for C++☆17Oct 3, 2018Updated 7 years ago
- The implementation of HawkEye, our research system: "HawkEye: Efficient Fine-grained OS Support for Huge Pages" from ASPLOS 2019.☆21Aug 5, 2021Updated 4 years ago
- ☆17Sep 15, 2021Updated 4 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- ☆24Nov 10, 2020Updated 5 years ago
- A new memory mapping interface for efficient direct user-space access to byte-addressable storage, published in MICRO2022.☆16Sep 29, 2022Updated 3 years ago
- SDAccel Examples☆360May 20, 2022Updated 4 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Attention Superoptimizer☆22Jan 20, 2025Updated last year
- FPGA version of Rodinia in HLS C/C++☆43Dec 24, 2020Updated 5 years ago
- An FPGA NES emulator designed by a high level synthesis (HLS)☆16Jun 11, 2017Updated 9 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Jan 28, 2025Updated last year
- Sample program to compare calculation performance between CPU and GPU☆16Oct 27, 2016Updated 9 years ago
- Linux source code for ISCA 2020 paper "Enhancing and Exploiting Contiguity for Fast Memory Virtualization"☆22Oct 31, 2020Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆173Nov 7, 2023Updated 2 years ago
- Pricing derivatives using the explicit finite-difference method☆13Jul 15, 2016Updated 10 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Provides an SSH server that enables rcon connections to configured game servers☆11Jul 24, 2019Updated 6 years ago
- ☆20Jul 26, 2021Updated 4 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 6 years ago
- ☆33Nov 13, 2020Updated 5 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- Highly-optimized spatially and temporally-blocked implementation of Diffusion 2D and 3D stencils for Intel FPGAs using OpenCL☆13Dec 25, 2023Updated 2 years ago
- OpenCL for Visual Studio Code☆39Jul 5, 2026Updated 2 weeks ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)☆11May 25, 2016Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The OpenDwarfs project provides a benchmark suite consisting of different computation/communication idioms, i.e., dwarfs, for state-of-ar…☆102Sep 18, 2019Updated 6 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- The codebase that computed the Ninth Dedekind Number☆13Jan 18, 2026Updated 6 months ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆387Jan 20, 2025Updated last year
- ☆14Feb 14, 2022Updated 4 years ago
- MLIR tools and dialect for GraphBLAS☆18Mar 30, 2022Updated 4 years ago