aeonstasis / sssp-fpga
Single-source shortest paths accelerated with AWS F1 FPGA
☆14Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for sssp-fpga
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- CAPI SNAP Framework Hardware and Software☆108Updated 3 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆21Updated 4 years ago
- ☆44Updated 4 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 4 months ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆47Updated 4 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆30Updated last year
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Centaur, a framework for hybrid CPU-FPGA databases☆26Updated 7 years ago
- Hybrid Threading Tool Set☆14Updated 4 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆64Updated 6 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 3 months ago
- ☆57Updated last year
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆81Updated 3 weeks ago
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆71Updated 2 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆43Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆64Updated 2 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- Distributed Accelerator OS☆60Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- Simple hash table on Verilog (SystemVerilog)☆47Updated 8 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆184Updated 6 months ago
- AMD OpenNIC driver includes the Linux kernel driver☆55Updated 7 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- HLS-based Graph Processing Framework on FPGAs☆139Updated 2 years ago