Alternatives and similar repositories for sssp-fpga

Users that are interested in sssp-fpga are comparing it to the libraries listed below

• SwarmArch / chronos
  The Chronos FPGA Framework to accelerate ordered applications
  ☆22Updated 4 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 3 months ago
• Xilinx / Get_Moving_With_Alveo
  For publishing the source for UG1352 "Get Moving with Alveo"
  ☆51Updated 4 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆47Updated 9 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆65Updated 6 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 8 months ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆87Updated 2 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆208Updated last year
• open-power / snap
  CAPI SNAP Framework Hardware and Software
  ☆110Updated 4 years ago
• zslwyuan / Hi-DMM
  Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)
  ☆25Updated 6 years ago
• OCT-FPGA / OCT-Tutorials
  ☆30Updated 7 months ago
• Xilinx / Vitis-AWS-F1-Developer-Labs
  ☆44Updated 4 years ago
• Essenceia / Nasdaq-HFT-FPGA
  RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
  ☆41Updated last year
• fpgasystems / davos
  Distributed Accelerator OS
  ☆62Updated 3 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆108Updated this week
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆36Updated last year
• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆31Updated 2 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆41Updated this week
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆49Updated 9 years ago
• fpgasystems / Centaur
  Centaur, a framework for hybrid CPU-FPGA databases
  ☆27Updated 8 years ago
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆48Updated 6 years ago
• TonyBrewer / OpenHT
  Hybrid Threading Tool Set
  ☆15Updated 4 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆149Updated 9 months ago