aeonstasis / sssp-fpgaLinks
Single-source shortest paths accelerated with AWS F1 FPGA
☆14Updated 7 years ago
Alternatives and similar repositories for sssp-fpga
Users that are interested in sssp-fpga are comparing it to the libraries listed below
Sorting:
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 10 months ago
- CAPI SNAP Framework Hardware and Software☆110Updated 4 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆226Updated last year
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆134Updated 4 years ago
- The Task Parallel System Composer (TaPaSCo)☆114Updated 3 weeks ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆73Updated last year
- ☆26Updated 4 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆42Updated 7 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- VNx: Vitis Network Examples☆155Updated 3 months ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆53Updated last year
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 7 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- A home for Genesis2 sources.☆43Updated 5 months ago
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 5 years ago
- ☆47Updated 5 years ago
- Open Programmable Acceleration Engine☆266Updated 4 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆18Updated 7 years ago
- Hybrid Threading Tool Set☆15Updated 5 years ago
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- ☆88Updated 2 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆70Updated 11 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆68Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Updated 5 years ago
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆62Updated last year