aeonstasis / sssp-fpgaLinks
Single-source shortest paths accelerated with AWS F1 FPGA
☆14Updated 7 years ago
Alternatives and similar repositories for sssp-fpga
Users that are interested in sssp-fpga are comparing it to the libraries listed below
Sorting:
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated 11 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆67Updated 6 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 4 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A home for Genesis2 sources.☆42Updated this week
- ☆44Updated 4 years ago
- Hybrid Threading Tool Set☆15Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆51Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- Distributed Accelerator OS☆63Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆67Updated 9 months ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- CAPI SNAP Framework Hardware and Software☆109Updated 4 years ago
- Spector: An OpenCL FPGA Benchmark Suite☆48Updated 6 years ago
- ☆19Updated 4 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 5 months ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆50Updated 6 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆81Updated last year
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 8 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 5 years ago
- ☆87Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago