xupgit / Embedded-System-Design-Flow-on-ZynqLinks
Updated version of the XUP Workshops
☆13Updated 7 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
Sorting:
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- ☆53Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆168Updated last year
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆103Updated 6 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- ☆60Updated last year
- Convolutional Neural Network Using High Level Synthesis☆89Updated 5 years ago
- Implementation of CNN using Verilog☆230Updated 8 years ago
- A collection of commonly asked RTL design interview questions☆35Updated 8 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆243Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- ☆69Updated 9 years ago
- RISC-V Integration for PYNQ☆177Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- round robin arbiter☆75Updated 11 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆232Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆94Updated 6 years ago
- AXI总线连接器☆105Updated 5 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 5 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- Pipeline FFT Implementation in Verilog HDL☆141Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆66Updated 7 years ago