Alternatives and similar repositories for Proteus:

Users that are interested in Proteus are comparing it to the libraries listed below

• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆67Updated 3 years ago
• UIUC-ChenLab / Nimblock
  ☆11Updated last year
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆41Updated 10 months ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆19Updated 2 months ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆13Updated 2 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• maestro-project / gamma
  ☆39Updated 7 months ago
• SFU-HiAccel / HiSpMV
  [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
  ☆8Updated 2 weeks ago
• UCLA-VAST / FlexCNN
  ☆71Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆84Updated 4 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆20Updated last month
• maestro-project / magma
  ☆16Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆47Updated this week
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆41Updated 2 years ago
• ucb-bar / dosa
  DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
  ☆13Updated 3 months ago
• hngenc / stellar
  ☆22Updated 2 months ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆17Updated 3 months ago
• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆19Updated 2 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• sfu-arch / SpGEMM
  ☆33Updated 3 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆79Updated last year
• maestro-project / confuciux
  ☆31Updated 3 years ago
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆17Updated 6 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆26Updated 3 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆85Updated 2 months ago