Huawei / fpga-accel
The official repository of the local FPGA Development Kit.
☆18Updated 5 years ago
Alternatives and similar repositories for fpga-accel:
Users that are interested in fpga-accel are comparing it to the libraries listed below
- ☆17Updated 5 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 7 years ago
- A platform for emulating Virtio devices with FPGAs☆25Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- PCIe DMA Subsystem based on Xilinx XAPP1171☆46Updated last year
- Computational Storage Device based on the open source project OpenSSD.☆19Updated 4 years ago
- ☆14Updated 3 years ago
- The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.☆50Updated 6 years ago
- ☆27Updated 4 years ago
- GUI for SymbiYosys☆13Updated 9 months ago
- Obsolete repository of official HUAWEI CLOUD FPGA Development Kit //github.com/huaweicloud/huaweicloud-fpga☆26Updated 6 years ago
- Public resources available for Xilinx MPSOC+ and SDSOC hardware☆17Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- ☆29Updated 2 years ago
- Distributed Accelerator OS☆60Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆43Updated 3 years ago
- An HLS-synthesizable Dynamic Memory Manager for FPGAs☆10Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆34Updated 11 months ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Updated 4 years ago
- IP Catalog for Raptor.☆10Updated last month
- ☆24Updated last year
- Linux kernel driver for memory mapped PCIe - FPGA communication.☆78Updated 10 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆15Updated 5 months ago
- Useful utilities for BAR projects☆30Updated last year
- Business Rule Engine Hardware Accelerator☆13Updated 4 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆44Updated 3 years ago
- ☆19Updated 6 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago