ATaylorCEngFIET / Building-Accelerated-Applications-with-VitisLinks
Support material for the Building Accelerated Applications with Vitis webinar series
☆17Updated 5 years ago
Alternatives and similar repositories for Building-Accelerated-Applications-with-Vitis
Users that are interested in Building-Accelerated-Applications-with-Vitis are comparing it to the libraries listed below
Sorting:
- AMD University Program HLS tutorial☆112Updated 11 months ago
- Vitis HLS Library for FINN☆208Updated last week
- ☆117Updated 4 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆201Updated 3 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆106Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆328Updated 8 months ago
- DPU on PYNQ☆228Updated 2 months ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- PYNQ Composabe Overlays☆73Updated last year
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 7 years ago
- SDAccel Development Environment Tutorials☆111Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆234Updated last month
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆80Updated 2 years ago
- ☆59Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Board files to build Ultra 96 PYNQ image☆157Updated 3 weeks ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- Library of approximate arithmetic circuits☆55Updated 3 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆26Updated 6 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆365Updated 8 months ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Verilog implementation of Softmax function☆70Updated 3 years ago