Support material for the Building Accelerated Applications with Vitis webinar series
☆17Sep 10, 2020Updated 5 years ago
Alternatives and similar repositories for Building-Accelerated-Applications-with-Vitis
Users that are interested in Building-Accelerated-Applications-with-Vitis are comparing it to the libraries listed below
Sorting:
- ☆13Sep 25, 2019Updated 6 years ago
- ☆117Jul 15, 2021Updated 4 years ago
- XRM (Xilinx FPGA Resource Manager) Document:☆25Nov 13, 2023Updated 2 years ago
- OpenCL FPGA Mining on Xilinx Alveo u200 u250 u280 FPGA Cards☆32Feb 15, 2019Updated 7 years ago
- 프론트 개발자 여자친구의 특별한 생일 이벤트 프로젝트 🎉☆10Oct 23, 2023Updated 2 years ago
- 한림대학교 오픈소스 SW 교육센터☆10Jan 30, 2020Updated 6 years ago
- Altair8800_Mister☆13Dec 9, 2025Updated 2 months ago
- This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.☆12Aug 1, 2024Updated last year
- Deep Learning Visualization Tools Using PyTorch☆11Feb 2, 2021Updated 5 years ago
- How to create, train and quantize network, then integrate it into pre/post image processing and generate CUDA C++ code for targeting Jets…☆12May 7, 2025Updated 10 months ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Jun 29, 2022Updated 3 years ago
- ☆12Apr 6, 2022Updated 3 years ago
- Griffinfly is COSIC's submission to the ZPRIZE competition under the category, Accelerating NTT Operations on an FPGA by Michiel Van Beir…☆11Feb 13, 2023Updated 3 years ago
- Updated version of the XUP Workshops☆12Aug 10, 2018Updated 7 years ago
- ☆13Oct 6, 2022Updated 3 years ago
- AMD University Program HLS tutorial☆123Oct 28, 2024Updated last year
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- ☆13Oct 27, 2020Updated 5 years ago
- Nexus Miner for Hash channel with FPGA/GPU/CPU pool and solo.☆12Dec 21, 2024Updated last year
- ☆19Nov 26, 2025Updated 3 months ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Jul 24, 2024Updated last year
- Vitis 部署加速器工作流介绍☆11Jan 10, 2025Updated last year
- Notebooks for the HE introduction☆10Sep 11, 2020Updated 5 years ago
- R-package: Bayesian variable selection, model choice, and regularized estimation for (spatial) generalized additive mixed regression …☆14Oct 22, 2024Updated last year
- simplest online-softmax notebook for explain Flash Attention☆16Jan 27, 2026Updated last month
- Co-processor for whole genome alignment☆13Jun 6, 2020Updated 5 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- Supplementary Material to accompany the paper, DJ Warne, SA Sisson, C Drovandi (2019) Acceleration of expensive computations in Bayesian…☆13Oct 23, 2020Updated 5 years ago
- SDAccel Development Environment Tutorials☆109Apr 8, 2020Updated 5 years ago
- genome sequence alignment☆14Oct 9, 2019Updated 6 years ago
- ☆13Sep 10, 2018Updated 7 years ago
- gemc website:☆15Feb 7, 2025Updated last year
- nnq_cnd_study stands for Neural Network Quantization & Compact Networks Design Study☆13Aug 31, 2020Updated 5 years ago
- For publishing the source for UG1352 "Get Moving with Alveo"☆50Jun 17, 2020Updated 5 years ago
- RedEye is a vision sensor designed to execute early stages of a deep convolutional neural network (ConvNet) in the analog domain. This re…☆14Dec 16, 2016Updated 9 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Design for using Ethernet on the ZCU102 development board☆15Dec 18, 2019Updated 6 years ago
- ☆15Jul 25, 2017Updated 8 years ago
- A language built atop the Sparse Synchronous Model☆18Dec 23, 2023Updated 2 years ago