Alternatives and similar repositories for ISPD24_contest

Users that are interested in ISPD24_contest are comparing it to the libraries listed below

• cuhk-eda / cu-gr-2
  ☆47Updated last year
• bu-icsg / TAP-2.5D
  ☆34Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆139Updated 4 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆63Updated 4 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆78Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆132Updated last year
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆52Updated 11 months ago
• uvahotspot / HotSpot
  HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
  ☆130Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆57Updated 4 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆63Updated last month
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆29Updated last year
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆52Updated 4 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆43Updated last year
• VidyaChhabria / ThermEDGe-and-IREDGe
  Encoder-decoder based generative networks for static and transient thermal analysis
  ☆21Updated 2 years ago
• liangrj2014 / ISPD25_contest
  ☆10Updated 6 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆157Updated 5 months ago
• ABKGroup / TritonRoute-WXL
  ☆34Updated 4 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆57Updated 9 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆91Updated 2 months ago
• EricLu1218 / Physical_Design_Automation
  NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…
  ☆42Updated last month
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆214Updated 2 weeks ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆239Updated 5 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆34Updated 3 months ago
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆15Updated 2 years ago
• NVlabs / INSTA
  ☆88Updated 3 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆22Updated 11 months ago
• CODA-Team / AnalogGym
  ☆61Updated last month