ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
☆66Mar 8, 2026Updated 5 months ago
Alternatives and similar repositories for Aries
Users that are interested in Aries are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆27May 18, 2025Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 5 months ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 3 weeks ago
- SCARIF is a tool to estimate the embodied carbon emissions of data center servers with accelerator hardware (GPUs, FPGAs, etc.)☆15Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆176Mar 12, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆147Updated this week
- ☆49Updated this week
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆32Nov 8, 2025Updated 9 months ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆20Dec 29, 2024Updated last year
- ☆13Apr 15, 2025Updated last year
- [FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs☆15Mar 26, 2025Updated last year
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- Fork of LLVM to support AMD AIEngine processors☆210Updated this week
- ☆63Mar 24, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Exact Symbolic Reasoning via Boolean Equality Saturation☆25Jan 7, 2026Updated 7 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆74Aug 1, 2025Updated last year
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆36Jun 3, 2026Updated 3 months ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆409Updated this week
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago
- A compiler for lowering quantized ML models to AMD AI Engine (AIE) firmware.☆21Updated this week
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆686Updated this week
- The missing pieces (as far as boilerplate reduction goes) of the upstream MLIR python bindings.☆118Mar 4, 2026Updated 5 months ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 3 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆34Nov 12, 2024Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs☆25Feb 14, 2023Updated 3 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆35Apr 11, 2024Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆302May 15, 2024Updated 2 years ago
- AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration (SC25)☆25Apr 14, 2026Updated 4 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 7 months ago
- ASTER 💫 : Assembly Tooling and Representations☆34Jul 1, 2026Updated 2 months ago
- Mapper for digital PIM architectures☆31Sep 1, 2025Updated last year
- ☆17Mar 26, 2025Updated last year
- C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!☆624Jun 19, 2025Updated last year
- An experimental project to bring MLIR to P4C.☆16Updated this week
- Ideas for P4 Projects.☆15Sep 18, 2024Updated last year