arc-research-lab / AriesLinks
ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)
☆52Updated last week
Alternatives and similar repositories for Aries
Users that are interested in Aries are comparing it to the libraries listed below
Sorting:
- ☆120Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆31Updated last year
- ☆60Updated 9 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 4 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆177Updated 2 weeks ago
- EQueue Dialect☆41Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- Allo Accelerator Design and Programming Framework☆313Updated this week
- ☆108Updated last year
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆13Updated last year
- ☆22Updated last week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆67Updated 2 weeks ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆49Updated 2 weeks ago
- ☆62Updated last week
- ☆40Updated 8 months ago
- agile hardware-software co-design☆52Updated 4 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆81Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated last week
- Release of stream-specialization software/hardware stack.☆120Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- A Toy-Purpose TPU Simulator☆19Updated last year