Miscellaneous components for bluespec
☆11Nov 18, 2024Updated last year
Alternatives and similar repositories for bluelib
Users that are interested in bluelib are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- ☆10Jun 30, 2021Updated 4 years ago
- ☆17Jun 24, 2021Updated 4 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)☆11May 25, 2016Updated 9 years ago
- ☆12May 20, 2021Updated 4 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆13Jan 27, 2017Updated 9 years ago
- ☆11Jun 18, 2018Updated 7 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.☆15Nov 2, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Learn the Design of a 6-stage pipelined RISC-V CPU☆17Oct 22, 2025Updated 5 months ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆12Aug 21, 2023Updated 2 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆19Jun 16, 2022Updated 3 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Mar 22, 2022Updated 4 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 11 months ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- DEPRECATED: Use ghc-heap, ghc-heap-view in GHC 8.x instead.☆18Sep 17, 2016Updated 9 years ago
- ☆16Feb 7, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated last month
- ☆10Mar 18, 2020Updated 6 years ago
- A nix expression to create a netboot k8s cluster of qemu instances.☆16May 21, 2018Updated 7 years ago
- Rust types for the debug server protocol☆11Jul 7, 2019Updated 6 years ago
- I ❤︎ FEM: A finite element method demo in Umka and tophat☆18Jul 12, 2025Updated 8 months ago
- Regex Engine using SIMD and Roaring-Bitmaps☆11Dec 26, 2022Updated 3 years ago
- Scrape Pokémon data from Serebii.net 💾☆14Jul 6, 2024Updated last year
- ☆33Mar 20, 2025Updated last year
- A Rust library for talking to J-Link USB devices☆43Jan 4, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13May 21, 2017Updated 8 years ago
- A game development framework that provides basic tooling and a content authoring workflow☆58Nov 7, 2020Updated 5 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Jun 7, 2021Updated 4 years ago
- Bluespec BSV HLHDL tutorial☆111Mar 29, 2016Updated 9 years ago
- Simple Game Engine Focusing on Vulkan Ray Tracing☆57Nov 15, 2021Updated 4 years ago
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆13Jun 14, 2020Updated 5 years ago
- The NandBug Software☆13May 23, 2020Updated 5 years ago