Miscellaneous components for bluespec
☆11Nov 18, 2024Updated last year
Alternatives and similar repositories for bluelib
Users that are interested in bluelib are comparing it to the libraries listed below
Sorting:
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- ☆10Jun 30, 2021Updated 4 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- ☆12May 20, 2021Updated 4 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- ☆17Jun 24, 2021Updated 4 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated 2 weeks ago
- ☆33Mar 20, 2025Updated 11 months ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Jun 7, 2021Updated 4 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Mar 22, 2022Updated 3 years ago
- A Rust library for talking to J-Link USB devices☆42Jan 4, 2024Updated 2 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- ☆14Sep 25, 2013Updated 12 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- ☆11Feb 5, 2017Updated 9 years ago
- ☆10Mar 18, 2020Updated 5 years ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)☆11May 25, 2016Updated 9 years ago
- ☆10Dec 27, 2020Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- ☆11Dec 9, 2022Updated 3 years ago
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆15Feb 24, 2026Updated last week
- Self implementation of course projects for Computer Architecture 2022 Spring☆11Sep 17, 2022Updated 3 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- Rust types for the debug server protocol☆11Jul 7, 2019Updated 6 years ago
- 我的小窝, 装修全纪录☆11Apr 19, 2021Updated 4 years ago
- ☆15Dec 9, 2025Updated 2 months ago
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆17Oct 22, 2025Updated 4 months ago
- 用所有主流语言写一个小说爬虫☆10May 11, 2022Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆11Jun 25, 2025Updated 8 months ago
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13May 21, 2017Updated 8 years ago