openhwgroup / cv-hpdcache-verifView external linksLinks
Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
☆20Jan 6, 2026Updated last month
Alternatives and similar repositories for cv-hpdcache-verif
Users that are interested in cv-hpdcache-verif are comparing it to the libraries listed below
Sorting:
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 6 months ago
- ☆14Jun 7, 2021Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated this week
- Simple UVM environment for experimenting with Verilator.☆28Nov 3, 2025Updated 3 months ago
- Simple AMBA VIP, Include axi/ahb/apb☆31Jul 4, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Feb 5, 2026Updated last week
- Microarchitecture diagrams of several CPUs☆47Feb 7, 2026Updated last week
- my UVM training projects☆39Mar 14, 2019Updated 6 years ago
- Medium Access Control layer of 802.15.4☆13Nov 14, 2014Updated 11 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- msfinance offers Pythonic way to download market data from morningstar.com☆15Feb 15, 2025Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated 4 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Nov 17, 2022Updated 3 years ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆10Feb 6, 2026Updated last week
- RTLMeter benchmark suite☆29Jan 25, 2026Updated 3 weeks ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- A Python library used to transfer files with QR codes. Input a file, get QR code images. Print, email, or otherwise share your codes. Re-…☆10Sep 15, 2019Updated 6 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- PLT Redex models of LVar calculi☆10Apr 6, 2015Updated 10 years ago
- Sia GPU miner☆10Jul 20, 2016Updated 9 years ago
- Post-Silicon Validation Tool based on REVERSI☆12Dec 10, 2025Updated 2 months ago
- Documenting usage scenarios for WebView and the challenges they create☆12Mar 22, 2024Updated last year
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- SECD machine and Lispkit Lisp compiler, in Python☆14Oct 25, 2017Updated 8 years ago
- ML Basis for Poly/ML☆13Oct 18, 2025Updated 3 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- Tutorial on modeling with TLA+☆24Oct 7, 2025Updated 4 months ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Jan 2, 2022Updated 4 years ago
- Equivalence checking with Yosys☆58Feb 4, 2026Updated last week
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 6 months ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- Spike, a RISC-V ISA Simulator☆10Jan 22, 2026Updated 3 weeks ago
- Source code for student lectures on dependent type theory.☆12Jun 9, 2025Updated 8 months ago
- SiliconCompiler Design Gallery☆59Feb 5, 2026Updated last week
- Repo for CHERIoT-SAFE development FPGA platform☆19Updated this week