Alternatives and similar repositories for cv-hpdcache-verif

Users that are interested in cv-hpdcache-verif are comparing it to the libraries listed below

• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• chipsalliance / uvm-verilator
  ☆95Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆43Updated 7 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆82Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆61Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated last year
• chipsalliance / tilelink
  ☆30Updated 5 months ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆21Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 8 months ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• sequencer / arithmetic
  ☆33Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆94Updated 2 weeks ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 2 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆198Updated 3 weeks ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago