openhwgroup / cv-hpdcache-verifLinks
Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
☆19Updated last week
Alternatives and similar repositories for cv-hpdcache-verif
Users that are interested in cv-hpdcache-verif are comparing it to the libraries listed below
Sorting:
- Advanced Architecture Labs with CVA6☆72Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- A dynamic verification library for Chisel.☆159Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆43Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆113Updated 2 months ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆12Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month
- ☆12Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆259Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆40Updated 2 months ago
- An open-source UCIe controller implementation☆82Updated this week
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆57Updated 6 years ago
- A Chisel RTL generator for network-on-chip interconnects☆224Updated 2 months ago
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- ☆82Updated last year
- Vector processor for RISC-V vector ISA☆134Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆33Updated 9 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ☆52Updated last year