Alternatives and similar repositories for cv-hpdcache-verif

Users that are interested in cv-hpdcache-verif are comparing it to the libraries listed below

• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆70Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆158Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆92Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆232Updated 2 weeks ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated 5 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• chipsalliance / uvm-verilator
  ☆105Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 10 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• AmeerAbdelhadi / Multiported-RAM
  Modular Multi-ported SRAM-based Memory
  ☆31Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆110Updated last week
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆40Updated last year
• pulp-platform / fpu_ss
  CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
  ☆12Updated 2 months ago
• black-parrot / black-parrot-sim
  ☆12Updated last month
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 weeks ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆17Updated 3 weeks ago
• pulp-platform / fpu
  ☆56Updated 6 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆72Updated last week
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆29Updated 2 weeks ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆50Updated last year
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆38Updated 2 weeks ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆76Updated this week
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆18Updated this week
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆24Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆186Updated last month