openhwgroup / cv-hpdcache-verif
Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
☆11Updated 2 months ago
Alternatives and similar repositories for cv-hpdcache-verif:
Users that are interested in cv-hpdcache-verif are comparing it to the libraries listed below
- Open-source non-blocking L2 cache☆42Updated this week
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆40Updated 6 months ago
- chipyard in mill :P☆78Updated last year
- ☆92Updated last year
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- Simple UVM environment for experimenting with Verilator.☆20Updated this week
- Open-source high-performance non-blocking cache☆80Updated 2 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago
- ☆33Updated last month
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆92Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- This repo includes XiangShan's function units☆21Updated this week
- ☆84Updated this week
- Advanced Architecture Labs with CVA6☆58Updated last year
- Platform Level Interrupt Controller☆40Updated 11 months ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆19Updated 3 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 7 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- A Chisel RTL generator for network-on-chip interconnects☆195Updated last month
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆53Updated last week
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week