michaelehab / AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
☆81Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for AES-Verilog
- ☆36Updated 3 years ago
- UVM and System Verilog Manuals☆36Updated 5 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆96Updated 9 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆71Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- round robin arbiter☆68Updated 10 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆120Updated 2 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆93Updated 6 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆44Updated last year
- VIP for AXI Protocol☆108Updated 2 years ago
- ☆15Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆32Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆89Updated 6 years ago