michaelehab / AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
☆86Updated 2 years ago
Alternatives and similar repositories for AES-Verilog:
Users that are interested in AES-Verilog are comparing it to the libraries listed below
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- ☆129Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆57Updated 11 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆52Updated 9 months ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆80Updated last year
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 9 months ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆100Updated 11 months ago
- round robin arbiter☆70Updated 10 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆77Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆62Updated last year
- ☆16Updated last year
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- ☆38Updated 3 years ago
- AXI DMA 32 / 64 bits☆103Updated 10 years ago