sarthak268 / Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
☆23Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for Embedded_Logic_and_Design
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆51Updated last year
- opensource EDA tool flor VLSI design☆29Updated last year
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- Repository for system verilog labs from cadence☆10Updated 4 years ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- ☆16Updated last year
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆40Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- Single Cycle MIPS Pipelined Processor using Verilog☆13Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- FPGA Design of a Neural Network for Color Detection☆72Updated 6 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆96Updated 9 months ago
- Lecture about FIR filter on an FPGA☆13Updated 6 months ago
- Single Cycle RISC MIPS Processor☆30Updated 3 years ago
- FFT algorithm for fpga☆18Updated 3 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆81Updated 2 years ago
- ☆26Updated 7 months ago
- ☆13Updated 2 years ago
- ☆16Updated 10 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- UVM and System Verilog Manuals☆36Updated 5 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆39Updated 4 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 5 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆98Updated 2 years ago
- ☆40Updated last year
- ☆99Updated 10 months ago