prajwalgekkouga / AHB-to-APB-BridgeLinks
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
☆68Updated 3 years ago
Alternatives and similar repositories for AHB-to-APB-Bridge
Users that are interested in AHB-to-APB-Bridge are comparing it to the libraries listed below
Sorting:
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆101Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- VIP for AXI Protocol☆157Updated 3 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆112Updated 10 months ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆130Updated 7 years ago
- UVM examples and projects☆148Updated 4 months ago
- ☆51Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆156Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆86Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆38Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆51Updated 5 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆184Updated 7 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- This is the main repository for all the examples for the book Practical UVM☆207Updated 5 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- System Verilog using Functional Verification☆12Updated last year
- ☆16Updated last year
- UVM AHB VIP☆87Updated 2 months ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆17Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆161Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- Verification IP for I2C protocol☆49Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- This is a detailed SystemVerilog course☆126Updated 8 months ago
- Verification IP for APB protocol☆72Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆56Updated 5 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago