My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
☆186Jul 28, 2021Updated 4 years ago
Alternatives and similar repositories for FPGA_Book_Experiments
Users that are interested in FPGA_Book_Experiments are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆81Nov 15, 2021Updated 4 years ago
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆30Mar 18, 2023Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆81Nov 8, 2025Updated 7 months ago
- This repository contains all the needed source files for several examples from Pong Chu's book: "Pong P. Chu, FPGA Prototyping by VHDL Ex…☆10Apr 2, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆12Mar 18, 2014Updated 12 years ago
- This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.☆48Feb 22, 2017Updated 9 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆70Nov 2, 2021Updated 4 years ago
- example code for the logi-boards from pong chu HDL book☆30Sep 4, 2015Updated 10 years ago
- Verilog modules required to get the OV7670 camera working☆83Jul 26, 2018Updated 7 years ago
- Implementation of Sobel Filter in Verilog☆28Mar 10, 2017Updated 9 years ago
- Hardware interface for USB controller on DE2 FPGA Platform☆27Dec 24, 2021Updated 4 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open Source VLSI Tools☆32Feb 6, 2021Updated 5 years ago
- Designs for the Olimex iCE40HX1K-EVB board☆14Aug 14, 2017Updated 8 years ago
- World's first Nintendo 3DS emulator for Apple devices based on Citra.☆18Apr 7, 2023Updated 3 years ago
- Verilog digital signal processing components☆184Oct 30, 2022Updated 3 years ago
- This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image…☆14Jul 5, 2017Updated 8 years ago
- ☆11Nov 17, 2025Updated 7 months ago
- Lora SX1276/7/8 module driver interfacing with STM32F103C8 bluepill. Keil Software code with HAL library☆11Jun 1, 2021Updated 5 years ago
- ☆17Sep 16, 2022Updated 3 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆55Jan 4, 2022Updated 4 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆86Sep 17, 2022Updated 3 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆16Aug 6, 2025Updated 10 months ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆143Jul 31, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆61Aug 30, 2021Updated 4 years ago
- ☆15Sep 23, 2020Updated 5 years ago
- Verilog UART☆573Feb 27, 2025Updated last year
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆122Oct 2, 2019Updated 6 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆129Dec 17, 2023Updated 2 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆14Jul 24, 2020Updated 5 years ago
- ☆16Mar 27, 2024Updated 2 years ago