AngeloJacobo / FPGA_Book_ExperimentsLinks
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
☆130Updated 3 years ago
Alternatives and similar repositories for FPGA_Book_Experiments
Users that are interested in FPGA_Book_Experiments are comparing it to the libraries listed below
Sorting:
- ☆93Updated last year
- Verilog UART☆165Updated 11 years ago
- Basic RISC-V Test SoC☆125Updated 6 years ago
- Verilog digital signal processing components☆139Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 6 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆97Updated 2 weeks ago
- SystemVerilog Tutorial☆149Updated 3 weeks ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆168Updated last week
- Verilog HDL files☆141Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆91Updated last year
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆62Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆123Updated last year
- Verilog implementation of multi-stage 32-bit RISC-V processor☆106Updated 4 years ago
- A simple implementation of a UART modem in Verilog.☆134Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆105Updated last year
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆105Updated this week
- ☆159Updated 2 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- This repo provide an index of VLSI content creators and their materials☆150Updated 9 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆129Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆102Updated 9 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Verilog implementation of a RISC-V core☆117Updated 6 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆248Updated 10 months ago
- Fixed Point Math Library for Verilog☆131Updated 10 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆236Updated this week
- This repository contains the design files of RISC-V Single Cycle Core☆47Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago