the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
☆48Jul 18, 2020Updated 5 years ago
Alternatives and similar repositories for Traffic-Light-Controller-using-Verilog
Users that are interested in Traffic-Light-Controller-using-Verilog are comparing it to the libraries listed below
Sorting:
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Nov 30, 2022Updated 3 years ago
- Verilog Project☆20Aug 30, 2021Updated 4 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆13Jun 13, 2021Updated 4 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆61Nov 25, 2020Updated 5 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆139Apr 3, 2020Updated 5 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆26Jun 10, 2018Updated 7 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆132Jul 31, 2022Updated 3 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆228May 20, 2025Updated 9 months ago
- Implementing Different Adder Structures in Verilog☆74Sep 3, 2019Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆40Jun 24, 2020Updated 5 years ago
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆146Jul 17, 2022Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆181Jan 29, 2024Updated 2 years ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆14Dec 15, 2023Updated 2 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- ☆116Dec 24, 2023Updated 2 years ago
- A real time microservices project using spring boot and spring cloud technologies☆16Apr 1, 2023Updated 2 years ago
- deltaV is a bare-metal hypervisor. (Raspberry Pi-3B) [ARMv8-A]☆14May 12, 2024Updated last year
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- ☆16Mar 27, 2024Updated last year
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆13Dec 29, 2022Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated last month
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆13Sep 18, 2025Updated 5 months ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- The project here contains the baseband simulation the satellite communication system with DVB-S standards.☆19Dec 14, 2019Updated 6 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Model LLM inference on single-core dataflow accelerators☆18Dec 16, 2025Updated 2 months ago