the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
☆48Jul 18, 2020Updated 5 years ago
Alternatives and similar repositories for Traffic-Light-Controller-using-Verilog
Users that are interested in Traffic-Light-Controller-using-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Nov 30, 2022Updated 3 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆37Jan 10, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆63Nov 25, 2020Updated 5 years ago
- Verilog Project☆21Aug 30, 2021Updated 4 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆13Jun 13, 2021Updated 4 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆140Apr 3, 2020Updated 5 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆27Jun 10, 2018Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆75Sep 3, 2019Updated 6 years ago
- Hardware Viterbi Decoder in verilog☆31May 28, 2019Updated 6 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆146Jul 17, 2022Updated 3 years ago
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆183Jan 29, 2024Updated 2 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Remote robot using STM32, ESP8266 and Android☆15Jul 12, 2025Updated 8 months ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Image Processing Toolbox in Verilog using Basys3 FPGA☆229May 20, 2025Updated 10 months ago
- 4 bit CPU (logisim, verilog)☆14Feb 24, 2026Updated last month
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- ☆18Jun 12, 2023Updated 2 years ago
- Verilog implementation of 74181 ALU chip☆12Oct 8, 2017Updated 8 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- Implementation of the paper "Deep Learning-Based Channel Estimation" (Lab based project)☆11Apr 20, 2020Updated 5 years ago
- ☆117Dec 24, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆14Dec 15, 2023Updated 2 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆15Dec 8, 2020Updated 5 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆39Jun 24, 2020Updated 5 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Ultrasonic Sensor Library For Proteus☆12Mar 8, 2020Updated 6 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago