Arjun-Narula / Traffic-Light-Controller-using-VerilogLinks
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
☆48Updated 5 years ago
Alternatives and similar repositories for Traffic-Light-Controller-using-Verilog
Users that are interested in Traffic-Light-Controller-using-Verilog are comparing it to the libraries listed below
Sorting:
- ☆117Updated last year
- ☆17Updated last year
- ☆44Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆165Updated last year
- ☆17Updated last year
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated 5 months ago
- Verilog Project☆19Updated 4 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆71Updated 3 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆122Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆161Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- opensource EDA tool flor VLSI design☆35Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆126Updated 3 years ago
- System Verilog using Functional Verification☆12Updated last year
- 100 Days of RTL☆403Updated last year
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆17Updated last year
- ☆22Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Updated 2 years ago
- ☆16Updated last year
- Image Processing Toolbox in Verilog using Basys3 FPGA☆220Updated 6 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆26Updated 10 months ago
- ☆10Updated 2 years ago
- Digital Design verilog tricky problems having industry standards☆28Updated 5 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆133Updated 4 years ago
- A complete UVM TB for verification of single port 64KB RAM☆16Updated 4 years ago