Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
☆41Updated 4 years ago
Alternatives and similar repositories for Traffic-Light-Controller-using-Verilog:
Users that are interested in Traffic-Light-Controller-using-Verilog are comparing it to the libraries listed below
- ☆16Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆115Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- ☆106Updated last year
- Architectural design of data router in verilog☆29Updated 5 years ago
- Single Cycle MIPS Pipelined Processor using Verilog☆13Updated 3 years ago
- Verilog Project☆10Updated 3 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆34Updated 5 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 7 months ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆10Updated 7 months ago
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- ☆9Updated 2 years ago
- ☆11Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆68Updated last year
- ☆39Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆27Updated 10 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆11Updated 2 months ago
- ☆22Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- ☆16Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆90Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- opensource EDA tool flor VLSI design☆32Updated last year
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆87Updated last year
- This repo provide an index of VLSI content creators and their materials☆146Updated 7 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆17Updated 11 months ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 3 years ago
- ☆41Updated 3 years ago