Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
☆41May 10, 2019Updated 7 years ago
Alternatives and similar repositories for VerilogHDL-Codes
Users that are interested in VerilogHDL-Codes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆145Apr 3, 2020Updated 6 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Jun 3, 2016Updated 10 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆38Jan 10, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Hardware Viterbi Decoder in verilog☆32May 28, 2019Updated 7 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 6 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- DDR2 memory controller written in Verilog☆84Feb 28, 2012Updated 14 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆21Nov 18, 2022Updated 3 years ago
- Many peripherals in Verilog ready to use☆41Dec 29, 2024Updated last year
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Jan 16, 2026Updated 6 months ago
- ☆18Jun 12, 2023Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆63Jan 20, 2026Updated 6 months ago
- A WIP library to control B1500 and similar testers via the VISA protocol, built on pyvisa☆11Nov 4, 2016Updated 9 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 8 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆20Aug 6, 2025Updated 11 months ago
- A collection of commonly asked RTL design interview questions☆57May 2, 2017Updated 9 years ago
- Verilog modules for beginners☆29May 27, 2022Updated 4 years ago
- ☆119Dec 24, 2023Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆53Feb 22, 2022Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆239May 20, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FPGA implementation of the hector_slam algorithm using only lidar data☆10Jul 3, 2022Updated 4 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆467Feb 13, 2026Updated 5 months ago
- Senior Design☆12Jan 26, 2025Updated last year
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- FPGA简单入门☆12Nov 17, 2020Updated 5 years ago