Alternatives and similar repositories for VerilogHDL-Codes

Users that are interested in VerilogHDL-Codes are comparing it to the libraries listed below

• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• shubhi704 / APB-Protocol
  ☆42Updated 3 years ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆26Updated 13 years ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆67Updated 5 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆10Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆21Updated 4 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆9Updated 2 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆55Updated last year
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆25Updated last year
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆17Updated 6 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆42Updated 6 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆17Updated last year
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆88Updated last year
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆50Updated 4 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆40Updated last year
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆54Updated 8 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆26Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆49Updated 3 years ago