Alternatives and similar repositories for Basic-SIMD-Processor-Verilog-Tutorial

Users that are interested in Basic-SIMD-Processor-Verilog-Tutorial are comparing it to the libraries listed below

• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆149Updated 9 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆99Updated 6 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆136Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆187Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆144Updated 7 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆153Updated 6 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆198Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆101Updated 5 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆267Updated last week
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆68Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆145Updated 6 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆80Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆74Updated 6 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆49Updated last year
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆201Updated 5 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆226Updated 3 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆134Updated 4 months ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆120Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆223Updated 5 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆147Updated 6 years ago