Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
☆160Jul 17, 2022Updated 4 years ago
Alternatives and similar repositories for Basic-SIMD-Processor-Verilog-Tutorial
Users that are interested in Basic-SIMD-Processor-Verilog-Tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Solution to COA LAB Assgn, IIT Kharagpur☆38Jan 10, 2019Updated 7 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆250May 20, 2025Updated last year
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆22Aug 6, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆235Jan 29, 2024Updated 2 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Overall multi-core SIMD microarchitecture☆25Aug 15, 2017Updated 9 years ago
- tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog☆68Jul 14, 2021Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆68Nov 25, 2020Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆33May 1, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆103Apr 30, 2019Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆78Sep 3, 2019Updated 7 years ago
- Hardware Viterbi Decoder in verilog☆31May 28, 2019Updated 7 years ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The Repository contains the code of various Digital Circuits☆14Aug 7, 2023Updated 3 years ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆76Sep 30, 2023Updated 3 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆28Jun 10, 2018Updated 8 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 10 years ago
- Dual-Core Out-of-Order MIPS CPU Design☆26May 8, 2025Updated last year
- opensource EDA tool flor VLSI design☆38Sep 17, 2023Updated 3 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆53Dec 3, 2023Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago