ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
☆42Updated last year
Related projects: ⓘ
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆20Updated last year
- ☆13Updated 6 months ago
- Simple Pipelined 32 bit RISC Processor☆13Updated 3 years ago
- Architectural design of data router in verilog☆26Updated 4 years ago
- ☆38Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆12Updated last year
- ☆16Updated 8 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆47Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆15Updated 11 months ago
- ☆35Updated 3 years ago
- ☆11Updated 11 months ago
- ☆16Updated 5 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated last year
- ☆12Updated 10 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆26Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆14Updated last year
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆11Updated last year
- ☆12Updated 7 months ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆62Updated last year
- ☆97Updated 8 months ago
- ☆16Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆20Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆31Updated 4 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆34Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆46Updated 2 years ago
- IEEE Executive project for the year 2021-2022☆8Updated last year
- An 8 input interrupt controller written in Verilog.☆24Updated 12 years ago
- ☆9Updated 2 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆41Updated 5 months ago