Alternatives and similar repositories for 100DaysofRTL

Users that are interested in 100DaysofRTL are comparing it to the libraries listed below

• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆24Updated 3 weeks ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆115Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated 2 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• shubhi704 / APB-Protocol
  ☆47Updated 4 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆16Updated 2 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆65Updated 2 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆12Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆42Updated 2 years ago
• raysalemi / Python4RTLVerification
  ☆165Updated 3 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated 2 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• Devipriya1921 / VSDBabySoC_ICC2
  ☆13Updated 3 years ago
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated last year
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆116Updated 3 years ago
• kerimturak / tcore-rv32imc
  ☆13Updated 5 months ago
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆24Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆26Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆82Updated last year
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• bpvsr / 2_Interview_Questions
  # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…
  ☆23Updated 2 months ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆33Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆44Updated 6 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆117Updated 6 months ago