nxbyte / Verilog-ProjectsLinks
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
☆114Updated 5 years ago
Alternatives and similar repositories for Verilog-Projects
Users that are interested in Verilog-Projects are comparing it to the libraries listed below
Sorting:
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- Basic RISC-V Test SoC☆140Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- Verilog digital signal processing components☆151Updated 2 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago
- Mathematical Functions in Verilog☆94Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆46Updated last year
- UVM and System Verilog Manuals☆44Updated 6 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆113Updated 3 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆154Updated 6 months ago
- Fixed Point Math Library for Verilog☆141Updated 11 years ago
- Verilog UART☆178Updated 12 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆48Updated 4 years ago
- ☆164Updated 2 years ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- A 2D convolution hardware implementation written in Verilog☆48Updated 4 years ago
- Verilog RTL Design☆44Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year
- SystemVerilog Tutorial☆166Updated 3 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆90Updated 2 years ago