nxbyte / Verilog-ProjectsLinks
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
☆119Updated 6 years ago
Alternatives and similar repositories for Verilog-Projects
Users that are interested in Verilog-Projects are comparing it to the libraries listed below
Sorting:
- Verilog digital signal processing components☆170Updated 3 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆120Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- Mathematical Functions in Verilog☆96Updated 4 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆121Updated 4 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆176Updated 2 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- A collection of commonly asked RTL design interview questions☆38Updated 8 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆144Updated 3 years ago
- Verilog/SystemVerilog Guide☆80Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆39Updated 6 years ago
- SystemVerilog Tutorial☆191Updated 2 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- DDR2 memory controller written in Verilog☆80Updated 13 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆145Updated 6 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆108Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆55Updated 8 years ago
- ☆175Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆83Updated 3 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago