Alternatives and similar repositories for 100DaysOfRTL:

Users that are interested in 100DaysOfRTL are comparing it to the libraries listed below

• Ummidichandrika / 100-Days-of-RTL
  ☆109Updated last year
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆237Updated 8 months ago
• raysalemi / Python4RTLVerification
  ☆154Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆419Updated 7 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆422Updated last week
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆120Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆601Updated this week
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆149Updated 8 months ago
• Abhishek-Sharma182005 / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆12Updated 3 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆525Updated 3 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆265Updated 2 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆568Updated last week
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆293Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆419Updated last month
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆394Updated 9 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆380Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆313Updated this week
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆185Updated 7 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆544Updated last week
• Prajwal-ECE / RTL-Coding
  ☆9Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆254Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆418Updated 2 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆324Updated 11 months ago
• alfadelta10010 / COD-Lab
  Instructions & Assignments for COD Lab - UE22EC352A
  ☆4Updated 5 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆521Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆475Updated 2 months ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆101Updated 11 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆199Updated last year
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆247Updated last month
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago