TheSUPERCD / 8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
☆55Updated 2 years ago
Alternatives and similar repositories for 8bit_MicroComputer_Verilog
Users that are interested in 8bit_MicroComputer_Verilog are comparing it to the libraries listed below
Sorting:
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- Implementing Different Adder Structures in Verilog☆67Updated 5 years ago
- opensource EDA tool flor VLSI design☆32Updated last year
- An 8 input interrupt controller written in Verilog.☆26Updated 13 years ago
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆43Updated last year
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆42Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆102Updated 9 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆76Updated last year
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆36Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆110Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆102Updated last year
- ☆12Updated last month
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆96Updated 2 years ago
- UVM and System Verilog Manuals☆42Updated 6 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Architectural design of data router in verilog☆30Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- ☆16Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆76Updated last year
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆11Updated 10 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆88Updated last year
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆58Updated 4 years ago