mongrelgem / Verilog-Adders
Implementing Different Adder Structures in Verilog
☆66Updated 5 years ago
Alternatives and similar repositories for Verilog-Adders:
Users that are interested in Verilog-Adders are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆12Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- my UVM training projects☆33Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- UVM and System Verilog Manuals☆41Updated 6 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A collection of commonly asked RTL design interview questions☆27Updated 8 years ago
- ☆32Updated 6 years ago
- Introductory course into static timing analysis (STA).☆90Updated last week
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 4 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- ☆17Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago