Alternatives and similar repositories for Verilog-Adders

Users that are interested in Verilog-Adders are comparing it to the libraries listed below

• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆37Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆97Updated 6 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆98Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆26Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆60Updated last week
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆75Updated 4 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆24Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆55Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆78Updated 7 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆45Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆54Updated last year
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆67Updated 9 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆80Updated 4 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆53Updated 4 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆53Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆126Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆140Updated 7 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆48Updated last year
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆115Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆37Updated 9 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago