Implementing Different Adder Structures in Verilog
☆74Sep 3, 2019Updated 6 years ago
Alternatives and similar repositories for Verilog-Adders
Users that are interested in Verilog-Adders are comparing it to the libraries listed below
Sorting:
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 7 years ago
- Implementation of different types of adder circuits☆16Jan 5, 2016Updated 10 years ago
- CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.☆21Apr 25, 2018Updated 7 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Nov 30, 2022Updated 3 years ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 7 months ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Jul 4, 2019Updated 6 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆29Feb 21, 2024Updated 2 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Feb 22, 2026Updated last week
- FIFO implementation with different clock domains for read and write.☆14Aug 17, 2021Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Dec 3, 2023Updated 2 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …