Alternatives and similar repositories for uart

Users that are interested in uart are comparing it to the libraries listed below

• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆132Updated 3 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆199Updated last year
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆102Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆134Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆115Updated 6 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆88Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆268Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated 2 months ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆126Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆450Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆302Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆74Updated 2 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆287Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆201Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆80Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆92Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆81Updated 5 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆322Updated 3 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆333Updated last year
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆53Updated 9 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆100Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆128Updated 10 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆231Updated 2 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆93Updated 6 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago