Verilog UART
☆195Jun 4, 2013Updated 12 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog UART☆552Feb 27, 2025Updated last year
- A simple implementation of a UART modem in Verilog.☆183Nov 10, 2021Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆116Apr 27, 2024Updated 2 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Oct 24, 2014Updated 11 years ago
- SPI Slave for FPGA in Verilog and VHDL☆231May 11, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- RTL Design and Verification☆21Jan 4, 2021Updated 5 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆697Feb 27, 2025Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆588Oct 10, 2021Updated 4 years ago
- Verilog implementation of a RISC-V core☆139Oct 11, 2018Updated 7 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- UART implementation using verilog☆36Feb 14, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- UART 16550 core☆39Jul 17, 2014Updated 11 years ago
- ☆56Jun 19, 2021Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆42Jun 19, 2024Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Various HDL (Verilog) IP Cores☆895Jul 1, 2021Updated 4 years ago
- A simple, basic, formally verified UART controller☆336Jan 29, 2024Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆317Sep 14, 2023Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆445Feb 13, 2026Updated 2 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- synthesiseable ieee 754 floating point library in verilog☆733Mar 13, 2023Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆86Feb 5, 2026Updated 2 months ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆145Oct 2, 2025Updated 6 months ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆369Mar 15, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆130Jul 11, 2025Updated 9 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- DPI module for UART-based console interaction with Verilator simulations☆25Oct 27, 2012Updated 13 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆294Feb 11, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆207Apr 8, 2026Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- Verilog SDRAM memory controller☆367May 13, 2017Updated 8 years ago
- ☆10Apr 8, 2021Updated 5 years ago