Verilog UART
☆203Jun 4, 2013Updated 13 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog UART☆587Feb 27, 2025Updated last year
- A simple implementation of a UART modem in Verilog.☆196Nov 10, 2021Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆121Apr 27, 2024Updated 2 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆19Oct 24, 2014Updated 11 years ago
- SPI Slave for FPGA in Verilog and VHDL☆233May 11, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- RTL Design and Verification☆23Jan 4, 2021Updated 5 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆730Feb 27, 2025Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆640Oct 10, 2021Updated 4 years ago
- Verilog implementation of a RISC-V core☆152Oct 11, 2018Updated 7 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- ☆58Jun 19, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated 2 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆51Jun 19, 2024Updated 2 years ago
- UART 16550 core☆44Jul 17, 2014Updated 12 years ago
- A simple, basic, formally verified UART controller☆353Jan 29, 2024Updated 2 years ago
- Various HDL (Verilog) IP Cores☆935Jul 1, 2021Updated 5 years ago
- Implemented The UART with FIFO☆16Jul 4, 2019Updated 7 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆484Sep 3, 2026Updated last month
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆352Sep 14, 2023Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆759Mar 13, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- UART implementation using verilog☆39Feb 14, 2023Updated 3 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆47Nov 24, 2014Updated 11 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated last month
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆417Aug 10, 2026Updated last month
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- DPI module for UART-based console interaction with Verilator simulations☆28Oct 27, 2012Updated 13 years ago
- Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.☆161Aug 21, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆301Feb 11, 2024Updated 2 years ago
- Verilog SDRAM memory controller☆383May 13, 2017Updated 9 years ago
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- ☆11Jul 12, 2023Updated 3 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,313Sep 18, 2021Updated 5 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆376Updated this week