jamieiles / uartLinks
Verilog UART
☆192Updated 12 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below
Sorting:
- A simple implementation of a UART modem in Verilog.☆171Updated 4 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- Simple 8-bit UART realization on Verilog HDL.☆114Updated last year
- Verilog digital signal processing components☆169Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆285Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆414Updated 4 months ago
- Verilog implementation of a RISC-V core☆135Updated 7 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- SPI Slave for FPGA in Verilog and VHDL☆220Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- AHB3-Lite Interconnect☆109Updated last year
- A simple, basic, formally verified UART controller☆323Updated 2 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆558Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- Arduino compatible Risc-V Based SOC☆160Updated last year
- Opensource DDR3 Controller☆413Updated 3 weeks ago
- Pipeline FFT Implementation in Verilog HDL☆159Updated 6 years ago
- DDR2 memory controller written in Verilog☆80Updated 13 years ago
- I2C controller core☆48Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- SPI Master for FPGA - VHDL and Verilog☆324Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated this week