Alternatives and similar repositories for uart

Users that are interested in uart are comparing it to the libraries listed below

• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆161Updated 6 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆168Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆216Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 9 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆394Updated 5 months ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆309Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆131Updated 7 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆330Updated last month
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆92Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆104Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆533Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆147Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆108Updated 4 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆157Updated last year
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆234Updated 3 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 9 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago