jamieiles / uart
Verilog UART
☆141Updated 11 years ago
Alternatives and similar repositories for uart:
Users that are interested in uart are comparing it to the libraries listed below
- Verilog digital signal processing components☆129Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Basic RISC-V Test SoC☆112Updated 5 years ago
- AHB3-Lite Interconnect☆84Updated 9 months ago
- SPI Slave for FPGA in Verilog and VHDL☆194Updated 9 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆144Updated this week
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆122Updated 4 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆97Updated 10 months ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆119Updated 3 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- SPI Master for FPGA - VHDL and Verilog☆270Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆307Updated 10 months ago
- An implementation of the CORDIC algorithm in Verilog.☆87Updated 6 years ago
- AXI interface modules for Cocotb☆237Updated last year
- Verilog SPI master and slave☆50Updated 9 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Fixed Point Math Library for Verilog☆124Updated 10 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆126Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- DDR2 memory controller written in Verilog☆73Updated 13 years ago
- WISHBONE SD Card Controller IP Core☆119Updated 2 years ago
- I2C controller core☆39Updated 2 years ago