Verilog UART
☆193Jun 4, 2013Updated 12 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below
Sorting:
- Verilog UART☆540Feb 27, 2025Updated last year
- A simple implementation of a UART modem in Verilog.☆177Nov 10, 2021Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆115Apr 27, 2024Updated last year
- Verilog uart receiver and transmitter modules for De0 Nano☆18Oct 24, 2014Updated 11 years ago
- SPI Slave for FPGA in Verilog and VHDL☆229May 11, 2024Updated last year
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- RTL Design and Verification☆18Jan 4, 2021Updated 5 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆686Feb 27, 2025Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆575Oct 10, 2021Updated 4 years ago
- Verilog implementation of a RISC-V core☆139Oct 11, 2018Updated 7 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 3 weeks ago
- UART implementation using verilog☆34Feb 14, 2023Updated 3 years ago
- UART 16550 core☆39Jul 17, 2014Updated 11 years ago
- ☆55Jun 19, 2021Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- A simple, basic, formally verified UART controller☆329Jan 29, 2024Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆308Sep 14, 2023Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆434Feb 13, 2026Updated last month
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- synthesiseable ieee 754 floating point library in verilog☆724Mar 13, 2023Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆138Oct 2, 2025Updated 5 months ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆359Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- DPI module for UART-based console interaction with Verilator simulations☆25Oct 27, 2012Updated 13 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆202Mar 6, 2026Updated 2 weeks ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆295Feb 11, 2024Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- Verilog SDRAM memory controller☆363May 13, 2017Updated 8 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- ☆10Apr 8, 2021Updated 4 years ago