Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus
☆16Oct 21, 2020Updated 5 years ago
Alternatives and similar repositories for PVS32_SoC
Users that are interested in PVS32_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- ☆19Oct 5, 2020Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆29Mar 22, 2012Updated 14 years ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 12 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- ☆11Jul 16, 2020Updated 5 years ago
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆17Apr 17, 2021Updated 5 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- ☆19Jul 21, 2020Updated 5 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 8 years ago
- Tutorial☆15Jun 13, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆11Jun 28, 2020Updated 5 years ago
- ☆14Oct 19, 2018Updated 7 years ago
- ☆22Sep 26, 2025Updated 8 months ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆14Nov 4, 2022Updated 3 years ago
- ☆11Jul 4, 2023Updated 2 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- ☆11Jul 16, 2020Updated 5 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- USB2.0 Device Controller IP Core☆16Aug 18, 2023Updated 2 years ago
- ☆13Nov 13, 2022Updated 3 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- ☆15Jul 17, 2020Updated 5 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆16Mar 25, 2025Updated last year
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago