Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus
☆16Oct 21, 2020Updated 5 years ago
Alternatives and similar repositories for PVS32_SoC
Users that are interested in PVS32_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- Hardware and Software Co-design implementations☆16Dec 5, 2019Updated 6 years ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 13 years ago
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆12May 14, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- ☆19Oct 5, 2020Updated 5 years ago
- ☆11Jul 16, 2020Updated 6 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- Tensor Processing Unit implementation in Verilog☆15Mar 18, 2025Updated last year
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- ☆14Jul 17, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11Jul 16, 2020Updated 6 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆18Apr 17, 2021Updated 5 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- USB2.0 Device Controller IP Core☆17Aug 18, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆11Jun 28, 2020Updated 6 years ago
- 简单易用的微信小程 序倒计时库☆15May 15, 2018Updated 8 years ago
- Peking University Embedded Microprocessor System Lesson’s all Homework☆10Dec 28, 2021Updated 4 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆14Jul 17, 2020Updated 6 years ago
- ☆19Jul 21, 2020Updated 6 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- ☆12Mar 10, 2023Updated 3 years ago