RV-AT / PVS32_SoCLinks
Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus
☆16Updated 5 years ago
Alternatives and similar repositories for PVS32_SoC
Users that are interested in PVS32_SoC are comparing it to the libraries listed below
Sorting:
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- ☆20Updated 3 years ago
- ☆22Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆28Updated 6 months ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- ☆13Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆34Updated 3 years ago
- ☆38Updated 10 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- AHB Bus lite v3.0☆16Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- an open source uvm verification platform for e200 (riscv)☆29Updated 7 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- AXI Interconnect☆54Updated 4 years ago
- ☆26Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Implementation of the PCIe physical layer☆60Updated 5 months ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- UVM candy lover testbench which uses YASA as simulation script☆17Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- ☆19Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated this week