rcetin / booth_wallace_multiplier

Related projects ⓘ

Alternatives and complementary repositories for booth_wallace_multiplier

• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆67Updated 6 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆93Updated 6 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆23Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆83Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆49Updated 7 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆54Updated 3 months ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆11Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆12Updated 3 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆29Updated 2 years ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆28Updated 4 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 7 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• Ams0x57 / Digital_Adders_Verilog
  32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…
  ☆24Updated 6 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆32Updated 4 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆19Updated 3 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆9Updated 4 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆58Updated 7 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆46Updated 3 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆67Updated 10 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆71Updated 5 years ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated 10 months ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆91Updated 4 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 5 years ago
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆22Updated last year