rcetin / booth_wallace_multiplierLinks
Booth encoded Wallace tree multiplier
☆17Updated 7 years ago
Alternatives and similar repositories for booth_wallace_multiplier
Users that are interested in booth_wallace_multiplier are comparing it to the libraries listed below
Sorting:
- study uvm step by step☆9Updated 6 years ago
- AXI Interconnect☆50Updated 3 years ago
- ☆34Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆22Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆104Updated 5 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- ☆25Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Sample UVM code for axi ram dut☆34Updated 3 years ago
- ☆20Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- IC Verification & SV Demo☆54Updated 3 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- ☆55Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆12Updated 2 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago