rcetin / booth_wallace_multiplier
Booth encoded Wallace tree multiplier
☆17Updated 6 years ago
Alternatives and similar repositories for booth_wallace_multiplier:
Users that are interested in booth_wallace_multiplier are comparing it to the libraries listed below
- ☆21Updated last year
- ☆31Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆62Updated 8 months ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆24Updated 6 years ago
- ☆63Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆18Updated 11 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- ☆9Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- ☆19Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆32Updated last year
- ☆27Updated 4 years ago
- SoC Based on ARM Cortex-M3☆30Updated 3 weeks ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆22Updated 2 years ago
- AIChip 2021 project, NCKU☆18Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 8 months ago