cterrill26 / FPGA_AudioVisualizer
Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA development board. Reads audio data from an external mic and displays the frequency components on a VGA monitor.
☆14Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for FPGA_AudioVisualizer
- AXI4-Stream FIR filter IP☆11Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆67Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆13Updated 5 years ago
- 基于FPGA的FFT☆12Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆35Updated 8 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Reed Solomon Encoder and Decoder Digital IP☆16Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆20Updated 4 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆29Updated 6 years ago
- FIR implemention with Verilog☆44Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- FPGA 同步FIFO与异步FIFO☆28Updated 5 years ago
- configurable cordic core in verilog☆47Updated 10 years ago
- Must-have verilog systemverilog modules☆25Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆40Updated 5 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆24Updated last year
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆28Updated 7 years ago
- ☆15Updated 6 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- FIR filter implementation☆21Updated 4 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- LMS sound filtering by Verilog☆35Updated 4 years ago
- FIR,FFT based on Verilog☆13Updated 6 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆35Updated 11 months ago
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆15Updated last year
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago